]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
cxgb4: Query firmware for T5 ULPTX MEMWRITE DSGL capabilities
authorKumar Sanghvi <kumaras@chelsio.com>
Tue, 18 Feb 2014 12:26:12 +0000 (17:56 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 18 Feb 2014 21:23:01 +0000 (16:23 -0500)
Query firmware to see whether we're allowed to use T5 ULPTX MEMWRITE DSGL
capabilities.  Also pass that information to Upper Layer Drivers via the
new (struct cxgb4_lld_info).ulptx_memwrite_dsgl boolean.

Based on original work by Casey Leedom <leedom@chelsio.com>

Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

index 028b5e540130f375ce781b88ae11bed34751aa48..944f2cbc1795c763c5494dd471a80e83d78f0936 100644 (file)
@@ -308,6 +308,7 @@ struct adapter_params {
        unsigned char bypass;
 
        unsigned int ofldq_wr_cred;
+       bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
 };
 
 #include "t4fw_api.h"
index 9222a8a8eec7b23d7b70c2d9900702d70b80dd9d..aeeaa06a7a34aeb6bb508ca6e10b312001c7dfc4 100644 (file)
@@ -3776,6 +3776,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
        lli.dbfifo_int_thresh = dbfifo_int_thresh;
        lli.sge_pktshift = adap->sge.pktshift;
        lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
+       lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
 
        handle = ulds[uld].add(&lli);
        if (IS_ERR(handle)) {
@@ -5380,6 +5381,21 @@ static int adap_init0(struct adapter *adap)
        val[0] = 1;
        (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
 
+       /*
+        * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
+        * capability.  Earlier versions of the firmware didn't have the
+        * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
+        * permission to use ULPTX MEMWRITE DSGL.
+        */
+       if (is_t4(adap->params.chip)) {
+               adap->params.ulptx_memwrite_dsgl = false;
+       } else {
+               params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
+               ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
+                                     1, params, val);
+               adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
+       }
+
        /*
         * Get device capabilities so we can determine what resources we need
         * to manage.
index 4dd0a82533e442f8b330c5ede554359ea450a087..e274a047528fca6ed11c9773db2d0a188e16da14 100644 (file)
@@ -253,6 +253,7 @@ struct cxgb4_lld_info {
                                             /* packet data */
        bool enable_fw_ofld_conn;            /* Enable connection through fw */
                                             /* WR */
+       bool ulptx_memwrite_dsgl;            /* use of T5 DSGL allowed */
 };
 
 struct cxgb4_uld_info {
index af6e12480e511a2e0ef47c06375b4b13c7123fb2..9cc973fbcf26761b322810fa91dcf61f528b3fc7 100644 (file)
@@ -932,6 +932,7 @@ enum fw_params_param_dev {
        FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
        FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
        FW_PARAMS_PARAM_DEV_CF = 0x0D,
+       FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
 };
 
 /*