Rename cpu_reset() to cpu_state_reset()

Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>

diff --git a/bsd-user/main.c b/bsd-user/main.c
index cdb0d0ac995ba74f00b35b524e1a4b7dd38689dc..c3af3950341c1ca20807992b3acfea7b27419b31 100644 (file)
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -917,7 +917,7 @@ int main(int argc, char **argv)
         exit(1);
     }
 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
-    cpu_reset(env);
+    cpu_state_reset(env);
 #endif
     thread_env = env;
 

diff --git a/cpu-all.h b/cpu-all.h
index f7f6e7acd376b247389cc2e49e81cd567adfca24..e831ae0acf68f76722d1cbbd6227a9a3fbd945ba 100644 (file)
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -433,7 +433,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask);
 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 
 void cpu_single_step(CPUState *env, int enabled);
-void cpu_reset(CPUState *s);
+void cpu_state_reset(CPUState *s);
 int cpu_is_stopped(CPUState *env);
 void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
 

diff --git a/cpu-exec.c b/cpu-exec.c
index 3d28053c559bef2b073dcaeb7e33ae64f03b9c0f..2bf1735c96f57fabac6f6782ae568254ee7411a8 100644 (file)
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -340,7 +340,7 @@ int cpu_exec(CPUState *env)
                     }
 #elif defined(TARGET_PPC)
                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
-                        cpu_reset(env);
+                        cpu_state_reset(env);
                     }
                     if (interrupt_request & CPU_INTERRUPT_HARD) {
                         ppc_hw_interrupt(env);

diff --git a/darwin-user/main.c b/darwin-user/main.c
index e1519c7d784b84b208826efadfbc40f27230c8d7..13c1f057c68410ba0c7964b49d39fc47c8f13c34 100644 (file)
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -858,7 +858,7 @@ int main(int argc, char **argv)
     /* NOTE: we need to init the CPU at this stage to get
        qemu_host_page_size */
     env = cpu_init(cpu_model);
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     printf("Starting %s with qemu\n----------------\n", filename);
 

diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index fc669100c5f3dc126cbbd8013a07369095889d95..23b3f0aad4960952a3da601f94c21a175bfaf904 100644 (file)
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -277,7 +277,7 @@ static void do_cpu_reset(void *opaque)
     CPUState *env = opaque;
     const struct arm_boot_info *info = env->boot_info;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     if (info) {
         if (!info->is_linux) {
             /* Jump to the entry point.  */

diff --git a/hw/armv7m.c b/hw/armv7m.c
index 6b805798e6dcbe8471c3e847b1f65176f4f6d571..9cf96f412be407771622de644e8611a574bba52b 100644 (file)
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
 
 static void armv7m_reset(void *opaque)
 {
-    cpu_reset((CPUState *)opaque);
+    cpu_state_reset((CPUState *)opaque);
 }
 
 /* Init CPU and memory for a v7-M based board.

diff --git a/hw/cris-boot.c b/hw/cris-boot.c
index 37894f8b53eaeedfff074aba7bb7f6eddc134e31..ade517dd256ba37db470ae927e26e274464b37dd 100644 (file)
--- a/hw/cris-boot.c
+++ b/hw/cris-boot.c
@@ -34,7 +34,7 @@ static void main_cpu_reset(void *opaque)
 
     li = env->load_info;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     if (!li) {
         /* nothing more to do.  */

diff --git a/hw/leon3.c b/hw/leon3.c
index 71d79a65a7ecd903977262592bf97f5a7896d75c..1dc5a02327ecfe8c365e90f904247abe25865187 100644 (file)
--- a/hw/leon3.c
+++ b/hw/leon3.c
@@ -51,7 +51,7 @@ static void main_cpu_reset(void *opaque)
     ResetData *s   = (ResetData *)opaque;
     CPUState  *env = s->env;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     env->halted = 0;
     env->pc     = s->entry;

diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index 3cdf120a144a7d3463801d4ee0a809329c595d33..51c8a0f91382cfa726972eb99222cc2c68945bad 100644 (file)
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -56,7 +56,7 @@ static void main_cpu_reset(void *opaque)
     ResetInfo *reset_info = opaque;
     CPUState *env = reset_info->env;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     /* init defaults */
     env->pc = (uint32_t)reset_info->bootstrap_pc;

diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c
index b2f96df344e1ddd81692d8954580a8ab558c132c..7ce04dcd63e6e993b6b25d44082edfca56132274 100644 (file)
--- a/hw/microblaze_boot.c
+++ b/hw/microblaze_boot.c
@@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->regs[5] = boot_info.cmdline;
     env->regs[7] = boot_info.fdt;
     env->sregs[SR_PC] = boot_info.bootstrap_pc;

diff --git a/hw/milkymist.c b/hw/milkymist.c
index eaef0c24c3a43d10e9a41daeecfaf021770a30ef..7ec65549f4750feba71392123d5e0a5e8ca7a2ad 100644 (file)
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -61,7 +61,7 @@ static void main_cpu_reset(void *opaque)
     ResetInfo *reset_info = opaque;
     CPUState *env = reset_info->env;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     /* init defaults */
     env->pc = reset_info->bootstrap_pc;

diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index efdfdc29ff6c4f865b9073be1c2895f0c89a0f52..dae488a9651aa0400a6ca2c15a490e527e9f18e0 100644 (file)
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -200,7 +200,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     /* TODO: 2E reset stuff */
     if (loaderparams.kernel_filename) {
         env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));

diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 2b4678e1708f1bb723a97a2a6003590b329cb894..d5f1b341b109d95df6b91e0024f1a04049d8b1c0 100644 (file)
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -51,7 +51,7 @@ enum jazz_model_e
 static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
-    cpu_reset(env);
+    cpu_state_reset(env);
 }
 
 static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 866699dbf0da517127366b6f63c93c86701e07a9..3335e11c44e8689220f7292771781deb2947b603 100644 (file)
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -745,7 +745,7 @@ static void malta_mips_config(CPUState *env)
 static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     /* The bootloader does not need to be rewritten as it is located in a
        read only location. The kernel location and the arguments table

diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index 76c95b2ec09f2679bdb4a43a2178447e9d8bec10..1fe4ac5b4dd1b58af4da93a911fc0943411b7b49 100644 (file)
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -107,7 +107,7 @@ static void main_cpu_reset(void *opaque)
     ResetData *s = (ResetData *)opaque;
     CPUState *env = s->env;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->active_tc.PC = s->vector & ~(target_ulong)1;
     if (s->vector & 1) {
         env->hflags |= MIPS_HFLAG_M16;

diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 83401f06486b39372be567a0fc80c63060baf6dd..96ad80883aba8493904b5bd76059a16ab181e7ac 100644 (file)
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -145,7 +145,7 @@ static void main_cpu_reset(void *opaque)
     ResetData *s = (ResetData *)opaque;
     CPUState *env = s->env;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->active_tc.PC = s->vector;
 }
 

diff --git a/hw/omap1.c b/hw/omap1.c
index 1aa5f2388b83fdde0de79a6b02a96fc8b8466a2e..5317b9be2b0c50ce1df5cb61577f355dc17f4f8d 100644 (file)
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque)
     omap_lpg_reset(mpu->led[0]);
     omap_lpg_reset(mpu->led[1]);
     omap_clkm_reset(mpu);
-    cpu_reset(mpu->env);
+    cpu_state_reset(mpu->env);
 }
 
 static const struct omap_map_s {

diff --git a/hw/omap2.c b/hw/omap2.c
index a6851b0fb08b234e80a950a5376adfb8013386cf..157defb39335d5578210028258df6b0822f14c82 100644 (file)
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque)
     omap_mcspi_reset(mpu->mcspi[1]);
     omap_i2c_reset(mpu->i2c[0]);
     omap_i2c_reset(mpu->i2c[1]);
-    cpu_reset(mpu->env);
+    cpu_state_reset(mpu->env);
 }
 
 static int omap2_validate_addr(struct omap_mpu_state_s *s,

diff --git a/hw/pc.c b/hw/pc.c
index bb9867b070375400946f3bab4ccc83ff8861a5ec..aca4460062fcda3b805a905954bc91739ea64346 100644 (file)
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -928,7 +928,7 @@ static void pc_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->halted = !cpu_is_bsp(env);
 }
 

diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index f86b16838a4d0736a2ea4247b4c42793e2ff52b5..835e36d49a830ac2e4e6dd6d3525be5b661f5865 100644 (file)
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->gpr[1] = (16<<20) - 8;
     env->gpr[3] = FDT_ADDR;
     env->nip = entry;

diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 26040ac3adf262111f768c82cfbe9e77a4bd6dff..23111620a30f382e34736c4aee08d71cd0c20eb2 100644 (file)
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -38,6 +38,13 @@
 #  define LOG_UIC(...) do { } while (0)
 #endif
 
+static void ppc4xx_reset(void *opaque)
+{
+    CPUState *env = opaque;
+
+    cpu_state_reset(env);
+}
+
 /*****************************************************************************/
 /* Generic PowerPC 4xx processor instantiation */
 CPUState *ppc4xx_init (const char *cpu_model,
@@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
     tb_clk->opaque = env;
     ppc_dcr_init(env, NULL, NULL);
     /* Register qemu callbacks */
-    qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+    qemu_register_reset(ppc4xx_reset, env);
 
     return env;
 }

diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 2fec5b4d67bd6c691aa31979f7e7d0567db4c92e..ee50652372c549d748c939e0236f5ae9297908e5 100644 (file)
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -121,6 +121,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
 }
 
+static void ppc_core99_reset(void *opaque)
+{
+    CPUState *env = opaque;
+
+    cpu_state_reset(env);
+}
+
 /* PowerPC Mac99 hardware initialisation */
 static void ppc_core99_init (ram_addr_t ram_size,
                              const char *boot_device,
@@ -166,7 +173,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
         }
         /* Set time-base frequency to 100 Mhz */
         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
-        qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+        qemu_register_reset(ppc_core99_reset, env);
     }
 
     /* allocate RAM */

diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 49c2c9795ebfa165b426a2810f89dea85fd5c47c..be701246272f79155788811c4aec0fffc59379b2 100644 (file)
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -65,6 +65,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
 }
 
+static void ppc_heathrow_reset(void *opaque)
+{
+    CPUState *env = opaque;
+
+    cpu_state_reset(env);
+}
+
 static void ppc_heathrow_init (ram_addr_t ram_size,
                                const char *boot_device,
                                const char *kernel_filename,
@@ -104,7 +111,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
         }
         /* Set time-base frequency to 16.6 Mhz */
         cpu_ppc_tb_init(env,  16600000UL);
-        qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+        qemu_register_reset(ppc_heathrow_reset, env);
     }
 
     /* allocate RAM */

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index dc9edd7bf50b13ee11636b7f4cb9f2e7993cdee5..6ccd6faedeedf4fb21a51edb5d118c41f777b2c7 100644 (file)
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -470,6 +470,13 @@ static void cpu_request_exit(void *opaque, int irq, int level)
     }
 }
 
+static void ppc_prep_reset(void *opaque)
+{
+    CPUState *env = opaque;
+
+    cpu_state_reset(env);
+}
+
 /* PowerPC PREP hardware initialisation */
 static void ppc_prep_init (ram_addr_t ram_size,
                            const char *boot_device,
@@ -524,7 +531,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
             /* Set time-base frequency to 100 Mhz */
             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
         }
-        qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+        qemu_register_reset(ppc_prep_reset, env);
     }
 
     /* allocate RAM */

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index d69f78cf33c56ebedd63f60b298e2fd98dcf0b14..752aed982a75d24d725216dceda7b9f2bd821a84 100644 (file)
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -198,7 +198,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     /* Secondary CPU starts in halted state for now. Needs to change when
        implementing non-kernel boot. */
@@ -211,7 +211,7 @@ static void mpc8544ds_cpu_reset(void *opaque)
     CPUState *env = opaque;
     struct boot_info *bi = env->load_info;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     /* Set initial guest state. */
     env->halted = 0;

diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 1ab27012c1d014fd2042fcf5e37a659b311baa88..f55287774adaa6b8a07b9ed67346dac33cf793ac 100644 (file)
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level)
     PXA2xxState *s = (PXA2xxState *) opaque;
 
     if (level && (s->pm_regs[PCFR >> 2] & 0x10)) {     /* GPR_EN */
-        cpu_reset(s->env);
+        cpu_state_reset(s->env);
         /* TODO: reset peripherals */
     }
 }

diff --git a/hw/r2d.c b/hw/r2d.c
index c80f9e3a2908eef655e783de5fc04e2065c05a5b..ae327a73f3128509bf46da5c854b445c5509f7c7 100644 (file)
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque)
     ResetData *s = (ResetData *)opaque;
     CPUState *env = s->env;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->pc = s->vector;
 }
 

diff --git a/hw/spapr.c b/hw/spapr.c
index dffb6a2a5048a37dd2ffabe2aed8de800859c8cf..3f9d87ceedde19d1a71cfca5b7a4f42b7cec4879 100644 (file)
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -502,6 +502,13 @@ static void spapr_reset(void *opaque)
 
 }
 
+static void spapr_cpu_reset(void *opaque)
+{
+    CPUState *env = opaque;
+
+    cpu_state_reset(env);
+}
+
 /* pSeries LPAR / sPAPR hardware init */
 static void ppc_spapr_init(ram_addr_t ram_size,
                            const char *boot_device,
@@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
         }
         /* Set time-base frequency to 512 MHz */
         cpu_ppc_tb_init(env, TIMEBASE_FREQ);
-        qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
+        qemu_register_reset(spapr_cpu_reset, env);
 
         env->hreset_vector = 0x60;
         env->hreset_excp_prefix = 0;

diff --git a/hw/sun4m.c b/hw/sun4m.c
index 99fb219b3a5f44b5dc2be74427a4b19afd66626d..4045740667377a903be19575a0427006a85f2a17 100644 (file)
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -283,7 +283,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->halted = 0;
 }
 
@@ -291,7 +291,7 @@ static void secondary_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->halted = 1;
 }
 

diff --git a/hw/sun4u.c b/hw/sun4u.c
index 423108f236078f9daf25cd01fc08f17317e7c4b8..8b043f2e5f503412f495fa50454c64ae76e96e40 100644 (file)
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -376,7 +376,7 @@ static void main_cpu_reset(void *opaque)
     CPUState *env = s->env;
     static unsigned int nr_resets;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
 
     cpu_timer_reset(env->tick);
     cpu_timer_reset(env->stick);

diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index f8d2b1be0441122e5ac213f13c0c6aef03d1a59c..e67249030b4052243486dd48358c9afa7ad42493 100644 (file)
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -109,7 +109,7 @@ static void main_cpu_reset(void *opaque)
     CPUState *env = opaque;
     struct boot_info *bi = env->load_info;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     /* Linux Kernel Parameters (passing device tree):
        *   r3: pointer to the fdt
        *   r4: 0

diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 26112c3eb0c6c8fc1d34b383ee5a65fc4abd99c1..80ba4d722aeab48b00814bd79cb4e85ade910e67 100644 (file)
--- a/hw/xtensa_lx60.c
+++ b/hw/xtensa_lx60.c
@@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
     return cpu_get_phys_page_debug(env, addr);
 }
 
-static void lx60_reset(void *env)
+static void lx60_reset(void *opaque)
 {
-    cpu_reset(env);
+    CPUState *env = opaque;
+
+    cpu_state_reset(env);
 }
 
 static void lx_init(const LxBoardDesc *board,
@@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board,
         /* Need MMU initialized prior to ELF loading,
          * so that ELF gets loaded into virtual addresses
          */
-        cpu_reset(env);
+        cpu_state_reset(env);
     }
 
     ram = g_malloc(sizeof(*ram));

diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
index 104e5dc6195aa0d82e27427ef9f44d7afb47ca08..445cfde217f951b000dada302c310861b3b51279 100644 (file)
--- a/hw/xtensa_sim.c
+++ b/hw/xtensa_sim.c
@@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
 
 static void sim_reset(void *env)
 {
-    cpu_reset(env);
+    cpu_state_reset(env);
 }
 
 static void sim_init(ram_addr_t ram_size,

diff --git a/linux-user/main.c b/linux-user/main.c
index bd4748941abd87135417a4b0350a882f91afe2f1..01129f2e3cb32dea6c8138c3cb63781cb27fd25f 100644 (file)
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3375,7 +3375,7 @@ int main(int argc, char **argv, char **envp)
         exit(1);
     }
 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
-    cpu_reset(env);
+    cpu_state_reset(env);
 #endif
 
     thread_env = env;

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 8a11213402554295ba7b76e01733e54ec11933cc..29888bd94b0a662000eed35457ac017c688dc9a4 100644 (file)
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4036,7 +4036,7 @@ static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp,
         /* we create a new CPU instance. */
         new_env = cpu_copy(env);
 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
-        cpu_reset(new_env);
+        cpu_state_reset(new_env);
 #endif
         /* Init regs that differ from the parent.  */
         cpu_clone_regs(new_env, newsp);

diff --git a/target-arm/helper.c b/target-arm/helper.c
index abe1c30d6a7b371f461bf8f387760d9b1f57d31d..13ff474c95981afaf5415d6bedee6aec0000f8e3 100644 (file)
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -278,7 +278,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     }
 }
 
-void cpu_reset(CPUARMState *env)
+void cpu_state_reset(CPUARMState *env)
 {
     uint32_t id;
     uint32_t tmp = 0;
@@ -416,7 +416,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
 
     env->cpu_model_str = cpu_model;
     env->cp15.c0_cpuid = id;
-    cpu_reset(env);
+    cpu_state_reset(env);
     if (arm_feature(env, ARM_FEATURE_NEON)) {
         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
                                  51, "arm-neon.xml", 0);

diff --git a/target-cris/translate.c b/target-cris/translate.c
index cbdc72c9b959e895ee49a823e44d3f33a3785cd1..f360c31e8ce4154cb8f581aea473e820f6927fd1 100644 (file)
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3513,7 +3513,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
 
        env->pregs[PR_VR] = vr_by_name(cpu_model);
        cpu_exec_init(env);
-       cpu_reset(env);
+    cpu_state_reset(env);
        qemu_init_vcpu(env);
 
        if (tcg_initialized)
@@ -3573,7 +3573,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
        return env;
 }
 
-void cpu_reset (CPUCRISState *env)
+void cpu_state_reset(CPUCRISState *env)
 {
        uint32_t vr;
 

diff --git a/target-i386/helper.c b/target-i386/helper.c
index f4f3c2726aacefab7774d0c654b18b03124e9cbd..140c696ffb4075d5c57012a7ebe6c29daab40864 100644 (file)
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -27,7 +27,7 @@
 //#define DEBUG_MMU
 
 /* NOTE: must be called outside the CPU execute loop */
-void cpu_reset(CPUX86State *env)
+void cpu_state_reset(CPUState *env)
 {
     int i;
 
@@ -1282,7 +1282,7 @@ void do_cpu_init(CPUState *env)
     int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
     uint64_t pat = env->pat;
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     env->interrupt_request = sipi;
     env->pat = pat;
     apic_init_reset(env->apic_state);

diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 2637c03c912ae3bfdf784c32601800ad0292b7b1..6834401d279ae8115c65c10695b7bc86900d0de3 100644 (file)
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -212,7 +212,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
     env->flags = 0;
 
     cpu_exec_init(env);
-    cpu_reset(env);
+    cpu_state_reset(env);
     qemu_init_vcpu(env);
 
     if (!tcg_initialized) {
@@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
     }
 }
 
-void cpu_reset(CPUState *env)
+void cpu_state_reset(CPUState *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index fa675bfca676216531ff2ccd360a3354c6c3caa8..3647366124e93544f81e6e0f6ae0e333d4ff2ba2 100644 (file)
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -143,7 +143,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
     return 0;
 }
 
-void cpu_reset(CPUM68KState *env)
+void cpu_state_reset(CPUM68KState *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -181,7 +181,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
         return NULL;
     }
 
-    cpu_reset(env);
+    cpu_state_reset(env);
     qemu_init_vcpu(env);
     return env;
 }

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 725c2ddf9b8d6de685aa8a5e18e3092863ce749d..e34e88d86c7bc8ccb9cffac33a83e19bf6e005e4 100644 (file)
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1897,7 +1897,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
     env = g_malloc0(sizeof(CPUState));
 
     cpu_exec_init(env);
-    cpu_reset(env);
+    cpu_state_reset(env);
     qemu_init_vcpu(env);
     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 
@@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
     return env;
 }
 
-void cpu_reset (CPUState *env)
+void cpu_state_reset(CPUState *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 722561695c32232a10f3d4d512d3d382bd2b1975..4d1cf9818dd8babe8f5010cc8f9e014100945837 100644 (file)
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -452,7 +452,7 @@ void do_interrupt (CPUState *env)
         set_hflags_for_handler(env);
         break;
     case EXCP_RESET:
-        cpu_reset(env);
+        cpu_state_reset(env);
         break;
     case EXCP_SRESET:
         env->CP0_Status |= (1 << CP0St_SR);

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8361d88aa8aa92df688d93cc9578ae57fb73a148..5061e782ed09d85c951ad20c4e5c29f7cf703f05 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12708,12 +12708,12 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
     fpu_init(env, def);
     mvp_init(env, def);
     mips_tcg_init();
-    cpu_reset(env);
+    cpu_state_reset(env);
     qemu_init_vcpu(env);
     return env;
 }
 
-void cpu_reset (CPUMIPSState *env)
+void cpu_state_reset(CPUMIPSState *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index bb76a8b9e0db78d445083dfa06ca8f0c8d61538d..f4552e8949760e34103468808df3469b72b5cfcc 100644 (file)
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3136,7 +3136,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
              TARGET_FMT_lx "\n", RA, msr);
 }
 
-void cpu_reset(CPUPPCState *env)
+void cpu_state_reset(CPUPPCState *env)
 {
     target_ulong msr;
 

diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index c0ec8908a674bb839267533ec17c21f070c6887e..1a1cc0eb152b0f8512c1d1e5f65f95e1f0968fb4 100644 (file)
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -95,7 +95,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
     env->cpu_model_str = cpu_model;
     env->cpu_num = cpu_num++;
     env->ext_index = -1;
-    cpu_reset(env);
+    cpu_state_reset(env);
     qemu_init_vcpu(env);
     return env;
 }
@@ -119,7 +119,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 
 #endif /* CONFIG_USER_ONLY */
 
-void cpu_reset(CPUS390XState *env)
+void cpu_state_reset(CPUS390XState *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index dd0ee4be93af8df8d879f3b55d086af450a24acb..c385de8b84002d3bf64cc849e1c44f7b8a394311 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -178,7 +178,7 @@ void cpu_dump_state(CPUState * env, FILE * f,
     }
 }
 
-void cpu_reset(CPUSH4State * env)
+void cpu_state_reset(CPUSH4State *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -279,7 +279,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
     env->movcal_backup_tail = &(env->movcal_backup);
     sh4_translate_init();
     env->cpu_model_str = cpu_model;
-    cpu_reset(env);
+    cpu_state_reset(env);
     cpu_register(env, def);
     qemu_init_vcpu(env);
     return env;

diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
index c7269b54a8973dde207a40125e402696f8896553..bb8b76178f36ce4c2b9cd07db3bac5ef500a03ee 100644 (file)
--- a/target-sparc/cpu_init.c
+++ b/target-sparc/cpu_init.c
@@ -23,7 +23,7 @@
 
 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
 
-void cpu_reset(CPUSPARCState *env)
+void cpu_state_reset(CPUSPARCState *env)
 {
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 42a559f756572f15fd20bb7c417ab6660ee56409..077c20a1bd528711410eaa1aa3dcf1c8459e28c0 100644 (file)
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -35,7 +35,7 @@
 
 static void reset_mmu(CPUState *env);
 
-void cpu_reset(CPUXtensaState *env)
+void cpu_state_reset(CPUXtensaState *env)
 {
     env->exception_taken = 0;
     env->pc = env->config->exception_vector[EXC_RESET];