When preparing the bitfield to write to HW register, the high-priority
queue error interrupt bit is set two times, and the beacon queue
TX-OK interrupt is not enabled.
Currently this have no functional impact because the high-priority
queue is not used at all, and the beacon queue is not used yet.
This patch removes high-priority queue bits and it adds the
beacon queue missing bit.
It removes also the management queue bits because it is not used.
This was found by static code analyzer.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
struct rtl8180_priv *priv = dev->priv;
if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
- rtl818x_iowrite32(priv, &priv->map->IMR, IMR_TMGDOK |
- IMR_TBDER | IMR_THPDER |
- IMR_THPDER | IMR_THPDOK |
+ rtl818x_iowrite32(priv, &priv->map->IMR,
+ IMR_TBDER | IMR_TBDOK |
IMR_TVODER | IMR_TVODOK |
IMR_TVIDER | IMR_TVIDOK |
IMR_TBEDER | IMR_TBEDOK |