.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
+ .broadcast_ctrl_reg = 0x06,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
+ .broadcast_ctrl_reg = 0x06,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
+ .broadcast_ctrl_reg = 0x06,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
+ .broadcast_ctrl_reg = 0x06,
.supports_mii = {false, false, true},
.supports_rmii = {false, false, true},
.internal_phy = {true, true, false},
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false,
false, true, false},
.supports_rmii = {false, false, false, false,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false,
false, true, true},
.supports_rmii = {false, false, false, false,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, true},
.supports_rmii = {false, false, true},
.supports_rgmii = {false, false, true},
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false,
false, true, true},
.supports_rmii = {false, false, false, false,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false, true, true},
.supports_rmii = {false, false, false, false, true, true},
.supports_rgmii = {false, false, false, false, true, true},
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
+ .broadcast_ctrl_reg = 0x0332,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
return ret;
}
+ /* set broadcast storm protection 10% rate */
+ regmap_update_bits(dev->regmap[1], dev->info->broadcast_ctrl_reg,
+ BROADCAST_STORM_RATE,
+ (BROADCAST_STORM_VALUE *
+ BROADCAST_STORM_PROT_RATE) / 100);
+
dev->dev_ops->config_cpu_port(ds);
dev->dev_ops->enable_stp_addr(dev);