Merge branch 'pci/enumeration'

- Rename pcibios_add_device() to pcibios_device_add() since it's called
  from pci_device_add() (Oliver O'Halloran)

- Don't try to enable AtomicOps on VFs, since they can only be enabled on
  the PF (Selvin Xavier)

* pci/enumeration:
  PCI: Do not enable AtomicOps on VFs
  PCI: Rename pcibios_add_device() to pcibios_device_add()

diff --combined drivers/pci/pci.c
index 17e4341df0ff3d6b3e20c7016e31cc015ec13ef9,e55d944ff30f17467e685be14904e68960d4b33e..3d98834ccc3a9f8ca52d1ef444ed20913ea5aecb
--- 1/drivers/pci/pci.c
--- 2/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@@ -1477,24 -1477,6 +1477,24 @@@ static int pci_save_pcie_state(struct p
        return 0;
  }
  
 +void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
 +{
 +#ifdef CONFIG_PCIEASPM
 +      struct pci_dev *bridge;
 +      u32 ctl;
 +
 +      bridge = pci_upstream_bridge(dev);
 +      if (bridge && bridge->ltr_path) {
 +              pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
 +              if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
 +                      pci_dbg(bridge, "re-enabling LTR\n");
 +                      pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
 +                                               PCI_EXP_DEVCTL2_LTR_EN);
 +              }
 +      }
 +#endif
 +}
 +
  static void pci_restore_pcie_state(struct pci_dev *dev)
  {
        int i = 0;
@@@ -1505,13 -1487,6 +1505,13 @@@
        if (!save_state)
                return;
  
 +      /*
 +       * Downstream ports reset the LTR enable bit when link goes down.
 +       * Check and re-configure the bit here before restoring device.
 +       * PCIe r5.0, sec 7.5.3.16.
 +       */
 +      pci_bridge_reconfigure_ltr(dev);
 +
        cap = (u16 *)&save_state->cap.data[0];
        pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
        pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
@@@ -2116,14 -2091,14 +2116,14 @@@ void pcim_pin_device(struct pci_dev *pd
  EXPORT_SYMBOL(pcim_pin_device);
  
  /*
-  * pcibios_add_device - provide arch specific hooks when adding device dev
+  * pcibios_device_add - provide arch specific hooks when adding device dev
   * @dev: the PCI device being added
   *
   * Permits the platform to provide architecture specific functionality when
   * devices are added. This is the default implementation. Architecture
   * implementations can override this.
   */
- int __weak pcibios_add_device(struct pci_dev *dev)
+ int __weak pcibios_device_add(struct pci_dev *dev)
  {
        return 0;
  }
@@@ -3744,6 -3719,14 +3744,14 @@@ int pci_enable_atomic_ops_to_root(struc
        struct pci_dev *bridge;
        u32 cap, ctl2;
  
+       /*
+        * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
+        * in Device Control 2 is reserved in VFs and the PF value applies
+        * to all associated VFs.
+        */
+       if (dev->is_virtfn)
+               return -EINVAL;
+ 
        if (!pci_is_pcie(dev))
                return -EINVAL;
  

diff --combined drivers/pci/probe.c
index 258350f80f6c7c621170c30c8da9c873a5c68429,2ba43b6adf315787a253095c8f122bb8bae9f197..240e4cf8c83e4e9634dbbeafca497e8310cd080b
--- 1/drivers/pci/probe.c
--- 2/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@@ -2168,21 -2168,9 +2168,21 @@@ static void pci_configure_ltr(struct pc
         * Complex and all intermediate Switches indicate support for LTR.
         * PCIe r4.0, sec 6.18.
         */
 -      if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
 -          ((bridge = pci_upstream_bridge(dev)) &&
 -            bridge->ltr_path)) {
 +      if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
 +              pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
 +                                       PCI_EXP_DEVCTL2_LTR_EN);
 +              dev->ltr_path = 1;
 +              return;
 +      }
 +
 +      /*
 +       * If we're configuring a hot-added device, LTR was likely
 +       * disabled in the upstream bridge, so re-enable it before enabling
 +       * it in the new device.
 +       */
 +      bridge = pci_upstream_bridge(dev);
 +      if (bridge && bridge->ltr_path) {
 +              pci_bridge_reconfigure_ltr(dev);
                pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
                                         PCI_EXP_DEVCTL2_LTR_EN);
                dev->ltr_path = 1;
@@@ -2462,7 -2450,7 +2462,7 @@@ static struct irq_domain *pci_dev_msi_d
        struct irq_domain *d;
  
        /*
-        * If a domain has been set through the pcibios_add_device()
+        * If a domain has been set through the pcibios_device_add()
         * callback, then this is the one (platform code knows best).
         */
        d = dev_get_msi_domain(&dev->dev);
@@@ -2530,7 -2518,7 +2530,7 @@@ void pci_device_add(struct pci_dev *dev
        list_add_tail(&dev->bus_list, &bus->devices);
        up_write(&pci_bus_sem);
  
-       ret = pcibios_add_device(dev);
+       ret = pcibios_device_add(dev);
        WARN_ON(ret < 0);
  
        /* Set up MSI IRQ domain */