drm/amd/display: do not reset lane count in EQ fallback

[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index e19447d526ea344c187dc46c48ca1fb431edec41..446e2933474cfb9221192f2a9d1674ba80fd4685 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting(
                                        current_link_setting->lane_count);
                } else if (!reached_minimum_link_rate
                                (current_link_setting->link_rate)) {
-                       current_link_setting->lane_count =
-                               initial_link_settings.lane_count;
                        current_link_setting->link_rate =
                                reduce_link_rate(
                                        current_link_setting->link_rate);