net: phy: add constants for fast retrain related register

Add the constants for 2.5G fast retrain capability
in 10G AN control register, fast retrain status and
control register and THP bypass register into mdio.h.

Signed-off-by: Luo Jie <luoj@codeaurora.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index bdf77dffa5a4f73bcc0df4d69285067ca34aeb9d..c54e6eae5366f673bf77148169ec6ec04332d253 100644 (file)
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -53,12 +53,14 @@
 #define MDIO_AN_EEE_LPABLE     61      /* EEE link partner ability */
 #define MDIO_AN_EEE_ADV2       62      /* EEE advertisement 2 */
 #define MDIO_AN_EEE_LPABLE2    63      /* EEE link partner ability 2 */
+#define MDIO_AN_CTRL2          64      /* AN THP bypass request control */
 
 /* Media-dependent registers. */
 #define MDIO_PMA_10GBT_SWAPPOL 130     /* 10GBASE-T pair swap & polarity */
 #define MDIO_PMA_10GBT_TXPWR   131     /* 10GBASE-T TX power control */
 #define MDIO_PMA_10GBT_SNR     133     /* 10GBASE-T SNR margin, lane A.
                                         * Lanes B-D are numbered 134-136. */
+#define MDIO_PMA_10GBR_FSRT_CSR        147     /* 10GBASE-R fast retrain status and control */
 #define MDIO_PMA_10GBR_FECABLE 170     /* 10GBASE-R FEC ability */
 #define MDIO_PCS_10GBX_STAT1   24      /* 10GBASE-X PCS status 1 */
 #define MDIO_PCS_10GBRT_STAT1  32      /* 10GBASE-R/-T PCS status 1 */
@@ -239,6 +241,9 @@
 #define MDIO_PMA_10GBR_FECABLE_ABLE    0x0001  /* FEC ability */
 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002  /* FEC error indic. ability */
 
+/* PMA 10GBASE-R Fast Retrain status and control register. */
+#define MDIO_PMA_10GBR_FSRT_ENABLE     0x0001  /* Fast retrain enable */
+
 /* PCS 10GBASE-R/-T status register 1. */
 #define MDIO_PCS_10GBRT_STAT1_BLKLK    0x0001  /* Block lock attained */
 
@@ -247,6 +252,7 @@
 #define MDIO_PCS_10GBRT_STAT2_BER      0x3f00
 
 /* AN 10GBASE-T control register. */
+#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020  /* Advertise 2.5GBASE-T fast retrain */
 #define MDIO_AN_10GBT_CTRL_ADV2_5G     0x0080  /* Advertise 2.5GBASE-T */
 #define MDIO_AN_10GBT_CTRL_ADV5G       0x0100  /* Advertise 5GBASE-T */
 #define MDIO_AN_10GBT_CTRL_ADV10G      0x1000  /* Advertise 10GBASE-T */
@@ -289,6 +295,9 @@
 #define MDIO_EEE_2_5GT         0x0001  /* 2.5GT EEE cap */
 #define MDIO_EEE_5GT           0x0002  /* 5GT EEE cap */
 
+/* AN MultiGBASE-T AN control 2 */
+#define MDIO_AN_THP_BP2_5GT    0x0008  /* 2.5GT THP bypass request */
+
 /* 2.5G/5G Extended abilities register. */
 #define MDIO_PMA_NG_EXTABLE_2_5GBT     0x0001  /* 2.5GBASET ability */
 #define MDIO_PMA_NG_EXTABLE_5GBT       0x0002  /* 5GBASET ability */