drm/msm/dsi: correct byte intf clock rate for 14nm DSI PHY

According to the vendor kernel, byte intf clock rate should be a half of
the byte clock only when DSI PHY version is above 2.0 (in other words,
10nm PHYs and later) and only if PHY is used in D-PHY mode. Currently
MSM DSI code handles only the second part of the clause (C-PHY vs
D-PHY), skipping DSI PHY version check, which causes issues on some of
14nm DSI PHY platforms (e.g. qcm2290).

Move divisor selection to DSI PHY code, pass selected divisor through
shared timings and set byte intf clock rate accordingly.

Cc: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6115P J606F
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/519006/
Link: https://lore.kernel.org/r/20230118130027.2345719-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 1a551cc0e889adfc4f7ff37356b31db6835e904c..bd3763a5d72340cd2c82d42f177cc02f35061ac0 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -141,6 +141,7 @@ struct msm_dsi_phy_shared_timings {
        u32 clk_post;
        u32 clk_pre;
        bool clk_pre_inc_by_2;
+       bool byte_intf_clk_div_2;
 };
 
 struct msm_dsi_phy_clk_request {

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index c8823e4115ea6d4aacf26b3bb91aa92d6ae53d5f..078462b74b5702764d1bd111e7ef5feee48b32af 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -122,6 +122,7 @@ struct msm_dsi_host {
        struct clk *byte_intf_clk;
 
        unsigned long byte_clk_rate;
+       unsigned long byte_intf_clk_rate;
        unsigned long pixel_clk_rate;
        unsigned long esc_clk_rate;
 
@@ -398,7 +399,6 @@ int msm_dsi_runtime_resume(struct device *dev)
 
 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
 {
-       unsigned long byte_intf_rate;
        int ret;
 
        DBG("Set clk rates: pclk=%d, byteclk=%lu",
@@ -418,13 +418,7 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
        }
 
        if (msm_host->byte_intf_clk) {
-               /* For CPHY, byte_intf_clk is same as byte_clk */
-               if (msm_host->cphy_mode)
-                       byte_intf_rate = msm_host->byte_clk_rate;
-               else
-                       byte_intf_rate = msm_host->byte_clk_rate / 2;
-
-               ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate);
+               ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate);
                if (ret) {
                        pr_err("%s: Failed to set rate byte intf clk, %d\n",
                               __func__, ret);
@@ -2393,6 +2387,10 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
                goto unlock_ret;
        }
 
+       msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate;
+       if (phy_shared_timings->byte_intf_clk_div_2)
+               msm_host->byte_intf_clk_rate /= 2;
+
        msm_dsi_sfpb_config(msm_host, true);
 
        ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators,

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 57445a5dc8167ba7d3e5e166ba230a44fdaf79f4..bb09cbe8ff86ba1f8fc6e71021eb3a016f9173c1 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -350,6 +350,8 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
                timing->shared_timings.clk_pre_inc_by_2 = 0;
        }
 
+       timing->shared_timings.byte_intf_clk_div_2 = true;
+
        timing->ta_go = 3;
        timing->ta_sure = 0;
        timing->ta_get = 4;
@@ -454,6 +456,8 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
        tmax = 255;
        timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin;
 
+       timing->shared_timings.byte_intf_clk_div_2 = true;
+
        DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
                timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
                timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,