drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chip

It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ca82fef421e177b68751773de45848fff7a2cb32..e41f489a8dc2fc88b86c77303dd29c06822fda71 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -836,6 +836,7 @@ struct amdgpu_device {
        dma_addr_t                      dummy_page_addr;
        struct amdgpu_vm_manager        vm_manager;
        struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
+       unsigned                        num_vmhubs;
 
        /* memory management */
        struct amdgpu_mman              mman;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f52823ffc7fdc4b56167f6d2a7a31e3751482797..0fd85cb15322fec9bd29689497d17ee9cb84530a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -603,6 +603,7 @@ static int gmc_v10_0_sw_init(void *handle)
        switch (adev->asic_type) {
        case CHIP_NAVI10:
        case CHIP_NAVI14:
+               adev->num_vmhubs = 2;
                /*
                 * To fulfill 4-level page support,
                 * vm size is 256TB (48bit), maximum size of Navi10/Navi14,

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ad45d633b147a563222c32a6843f960225d06f80..2afc37237ad31e8c286ecae04e941da8d73403c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -284,7 +284,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
-               for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
+               for (j = 0; j < adev->num_vmhubs; j++) {
                        hub = &adev->vmhub[j];
                        for (i = 0; i < 16; i++) {
                                reg = hub->vm_context0_cntl + i;
@@ -295,7 +295,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                }
                break;
        case AMDGPU_IRQ_STATE_ENABLE:
-               for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
+               for (j = 0; j < adev->num_vmhubs; j++) {
                        hub = &adev->vmhub[j];
                        for (i = 0; i < 16; i++) {
                                reg = hub->vm_context0_cntl + i;
@@ -419,7 +419,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
        const unsigned eng = 17;
        unsigned i, j;
 
-       for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+       for (i = 0; i < adev->num_vmhubs; ++i) {
                struct amdgpu_vmhub *hub = &adev->vmhub[i];
                u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 
@@ -980,6 +980,8 @@ static int gmc_v9_0_sw_init(void *handle)
        adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
        switch (adev->asic_type) {
        case CHIP_RAVEN:
+               adev->num_vmhubs = 2;
+
                if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
                        amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
                } else {
@@ -992,6 +994,8 @@ static int gmc_v9_0_sw_init(void *handle)
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_VEGA20:
+               adev->num_vmhubs = 2;
+
                /*
                 * To fulfill 4-level page support,
                 * vm size is 256TB (48bit), maximum size of Vega10,