/* shifts */
/* T1 based */
+
void OPPROTO op_shll_T1_im(void)
{
T1 = T1 << PARAM1;
T1 = (uint32_t)T1 >> PARAM1;
}
+void OPPROTO op_shrl_T1_0(void)
+{
+ T1 = 0;
+}
+
void OPPROTO op_sarl_T1_im(void)
{
T1 = (int32_t)T1 >> PARAM1;
}
+void OPPROTO op_sarl_T1_0(void)
+{
+ T1 = (int32_t)T1 >> 31;
+}
+
void OPPROTO op_rorl_T1_im(void)
{
int shift;
T1 = (uint32_t)T1 >> PARAM1;
}
+void OPPROTO op_shrl_T1_0_cc(void)
+{
+ env->CF = (T1 >> 31) & 1;
+ T1 = 0;
+}
+
void OPPROTO op_sarl_T1_im_cc(void)
{
env->CF = (T1 >> (PARAM1 - 1)) & 1;
T1 = (int32_t)T1 >> PARAM1;
}
+void OPPROTO op_sarl_T1_0_cc(void)
+{
+ env->CF = (T1 >> 31) & 1;
+ T1 = (int32_t)T1 >> 31;
+}
+
void OPPROTO op_rorl_T1_im_cc(void)
{
int shift;
T2 = (uint32_t)T2 >> PARAM1;
}
+void OPPROTO op_shrl_T2_0(void)
+{
+ T2 = 0;
+}
+
void OPPROTO op_sarl_T2_im(void)
{
T2 = (int32_t)T2 >> PARAM1;
}
+void OPPROTO op_sarl_T2_0(void)
+{
+ T2 = (int32_t)T2 >> 31;
+}
+
void OPPROTO op_rorl_T2_im(void)
{
int shift;
T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
}
+void OPPROTO op_rrxl_T2(void)
+{
+ T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31);
+}
+
/* T1 based, use T0 as shift count */
void OPPROTO op_shll_T1_T0(void)
gen_op_rorl_T1_im,
};
+static GenOpFunc *gen_shift_T1_0[4] = {
+ NULL,
+ gen_op_shrl_T1_0,
+ gen_op_sarl_T1_0,
+ gen_op_rrxl_T1,
+};
+
static GenOpFunc1 *gen_shift_T2_im[4] = {
gen_op_shll_T2_im,
gen_op_shrl_T2_im,
gen_op_rorl_T2_im,
};
+static GenOpFunc *gen_shift_T2_0[4] = {
+ NULL,
+ gen_op_shrl_T2_0,
+ gen_op_sarl_T2_0,
+ gen_op_rrxl_T2,
+};
+
static GenOpFunc1 *gen_shift_T1_im_cc[4] = {
gen_op_shll_T1_im_cc,
gen_op_shrl_T1_im_cc,
gen_op_rorl_T1_im_cc,
};
+static GenOpFunc *gen_shift_T1_0_cc[4] = {
+ NULL,
+ gen_op_shrl_T1_0_cc,
+ gen_op_sarl_T1_0_cc,
+ gen_op_rrxl_T1_cc,
+};
+
static GenOpFunc *gen_shift_T1_T0[4] = {
gen_op_shll_T1_T0,
gen_op_shrl_T1_T0,
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)
{
- int val, rm, shift;
+ int val, rm, shift, shiftop;
if (!(insn & (1 << 25))) {
/* immediate */
rm = (insn) & 0xf;
shift = (insn >> 7) & 0x1f;
gen_movl_T2_reg(s, rm);
+ shiftop = (insn >> 5) & 3;
if (shift != 0) {
- gen_shift_T2_im[(insn >> 5) & 3](shift);
+ gen_shift_T2_im[shiftop](shift);
+ } else if (shiftop != 0) {
+ gen_shift_T2_0[shiftop]();
}
if (!(insn & (1 << 23)))
gen_op_subl_T1_T2();
} else {
gen_shift_T1_im[shiftop](shift);
}
- } else if (shiftop == 3) {
- if (logic_cc)
- gen_op_rrxl_T1_cc();
- else
- gen_op_rrxl_T1();
+ } else if (shiftop != 0) {
+ if (logic_cc) {
+ gen_shift_T1_0_cc[shiftop]();
+ } else {
+ gen_shift_T1_0[shiftop]();
+ }
}
} else {
rs = (insn >> 8) & 0xf;