target-arm queue:
* support REFCNT register on integrator/cp board
* implement the A9MP's global timer
* add the 'virt' platform
* support '-cpu host' on KVM/ARM
* Cadence GEM ethernet device bugfixes
* Implement 32-bit ARMv8 VSEL, VMAXNM, VMINNM
* fix TTBCR write masking
* update 32 bit decoder to use new qemu_ld/st TCG opcodes
# gpg: Signature made Tue 10 Dec 2013 06:22:01 AM PST using RSA key ID
14360CDE
# gpg: Can't check signature: public key not found
# By Peter Crosthwaite (16) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-
20131210: (37 commits)
target-arm: fix TTBCR write masking
target-arm: Use new qemu_ld/st opcodes
target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.
target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
softfloat: Add minNum() and maxNum() functions to softfloat.
softfloat: Remove unused argument from MINMAX macro.
target-arm: Implement ARMv8 VSEL instruction.
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
net/cadence_gem: Don't rx packets when no rx buffer available
net/cadence_gem: Improve can_receive debug printfery
net/cadence_gem: Fix register w1c logic
net/cadence_gem: Fix small packet FCS stripping
net/cadence_gem: Fix rx multi-fragment packets
net/cadence_gem: Add missing VMSTATE_END_OF_LIST
net/cadence_gem: Implement SAR (de)activation
net/cadence_gem: Implement SAR match bit in rx desc
net/cadence_gem: Implement RX descriptor match mode flags
net/cadence_gem: Prefetch rx descriptors ASAP
net/cadence_gem: simplify rx buf descriptor walking
net/cadence_gem: Don't assert against 0 buffer address
...
Message-id:
1386686613-2390-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <aliguori@amazon.com>