drm/amdgpu: Use physical translation mode to access page table

On A+A platform, CPU write page directory and page table in cached
mode. So it is necessary for page table walker to snoop CPU cache.
This setting is necessary for page walker to snoop page directory
and page table data out of CPU cache.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 6ddd53ba8b777b3c3a272ff01a71c3063743cfe2..c6687c6cf03d3ee3513f97b3064c11e282deb5df 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -173,8 +173,13 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
        WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
 
        tmp = mmVM_L2_CNTL4_DEFAULT;
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+       if (adev->gmc.xgmi.connected_to_cpu) {
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+       } else {
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+       }
        WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index c3f3e755d4b7370b170128f81fe8ca7961a5cacf..08c50ce491e3ecee7cb003fd0fd53020661be921 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -178,8 +178,17 @@ static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
        WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
 
        tmp = regVM_L2_CNTL4_DEFAULT;
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+       if (adev->gmc.xgmi.connected_to_cpu) {
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
+                                   VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
+                                   VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+       } else {
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
+                                   VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
+                                   VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+       }
        WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
 }