]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/commitdiff
Merge tag 'juno-updates-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep...
authorOlof Johansson <olof@lixom.net>
Mon, 19 Jun 2017 03:55:51 +0000 (20:55 -0700)
committerOlof Johansson <olof@lixom.net>
Mon, 19 Jun 2017 03:55:51 +0000 (20:55 -0700)
ARMv8 Vexpress/Juno DT updates for v4.13

1. Adds support for Coresight CPU debug MMIO interface on all Juno variants.

2. Enables support for few SMMUs on Juno which were previously disabled
   waiting for IOMMU-backed DMA API support to be stabilised.

* tag 'juno-updates-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: enable some SMMUs
  arm64: dts: juno: add coresight CPU debug nodes

Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm64/boot/dts/arm/juno-base.dtsi
arch/arm64/boot/dts/arm/juno-r1.dts
arch/arm64/boot/dts/arm/juno-r2.dts
arch/arm64/boot/dts/arm/juno.dts

index bfe7d683a42e1b27b6e90997f9ebf18abb79afce..e8b7413ec890b8fc88f1fb62d691d7ffcdae8570 100644 (file)
@@ -53,7 +53,6 @@
                #global-interrupts = <1>;
                dma-coherent;
                power-domains = <&scpi_devpd 0>;
-               status = "disabled";
        };
 
        gic: interrupt-controller@2c010000 {
                };
        };
 
+       cpu_debug0: cpu_debug@22010000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x22010000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm0: etm@22040000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x22040000 0 0x1000>;
                };
        };
 
+       cpu_debug1: cpu_debug@22110000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x22110000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm1: etm@22140000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x22140000 0 0x1000>;
                };
        };
 
+       cpu_debug2: cpu_debug@23010000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23010000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm2: etm@23040000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23040000 0 0x1000>;
                };
        };
 
+       cpu_debug3: cpu_debug@23110000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23110000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm3: etm@23140000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23140000 0 0x1000>;
                };
        };
 
+       cpu_debug4: cpu_debug@23210000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23210000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm4: etm@23240000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23240000 0 0x1000>;
                };
        };
 
+       cpu_debug5: cpu_debug@23310000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23310000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm5: etm@23340000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23340000 0 0x1000>;
                             <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
                #iommu-cells = <1>;
                #global-interrupts = <1>;
-               status = "disabled";
        };
 
        smmu_hdlcd0: iommu@7fb20000 {
                             <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                #iommu-cells = <1>;
                #global-interrupts = <1>;
-               status = "disabled";
        };
 
        smmu_usb: iommu@7fb30000 {
                #iommu-cells = <1>;
                #global-interrupts = <1>;
                dma-coherent;
-               status = "disabled";
        };
 
        dma@7ff00000 {
index 0e8943ab94d77497ad28f6699e23d7bc4dec7958..aed6389468c4a1d386189265e2d7a0abe68f6b06 100644 (file)
 &stm_out_port {
        remote-endpoint = <&csys1_funnel_in_port0>;
 };
+
+&cpu_debug0 {
+       cpu = <&A57_0>;
+};
+
+&cpu_debug1 {
+       cpu = <&A57_1>;
+};
+
+&cpu_debug2 {
+       cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+       cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+       cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+       cpu = <&A53_3>;
+};
index 405e2fba025beeec73c8ba020fa2329f2438f533..b39b6d6ec5aa1be93c88e7a988bdbae3cfd40a9b 100644 (file)
 &stm_out_port {
        remote-endpoint = <&csys1_funnel_in_port0>;
 };
+
+&cpu_debug0 {
+       cpu = <&A72_0>;
+};
+
+&cpu_debug1 {
+       cpu = <&A72_1>;
+};
+
+&cpu_debug2 {
+       cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+       cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+       cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+       cpu = <&A53_3>;
+};
index 0220494c9b80222d742fb1285e52d1a01a7066ba..c9236c4b967d2f461b91730e0b8f3f941b32d307 100644 (file)
                };
        };
 };
+
+&cpu_debug0 {
+       cpu = <&A57_0>;
+};
+
+&cpu_debug1 {
+       cpu = <&A57_1>;
+};
+
+&cpu_debug2 {
+       cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+       cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+       cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+       cpu = <&A53_3>;
+};