ARM: dts: imx6ul: Add imx6ul-tempmon

This works identically to imx6sx-tempmon on both imx6ul and imx6ull.
It just needs to be defined in dts.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 2057ee695a664e7386675824ab296fa5621eb477..d5181f85ca9cafbba955ca1a3a6e5fbaedf9248f 100644 (file)
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -598,6 +598,15 @@
                                fsl,anatop = <&anatop>;
                        };
 
+                       tempmon: tempmon {
+                               compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
+                               interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               fsl,tempmon = <&anatop>;
+                               nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+                               nvmem-cell-names = "calib", "temp_grade";
+                               clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
+                       };
+
                        snvs: snvs@20cc000 {
                                compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
                                reg = <0x020cc000 0x4000>;
@@ -861,9 +870,19 @@
                        };
 
                        ocotp: ocotp-ctrl@21bc000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
                                compatible = "fsl,imx6ul-ocotp", "syscon";
                                reg = <0x021bc000 0x4000>;
                                clocks = <&clks IMX6UL_CLK_OCOTP>;
+
+                               tempmon_calib: calib@38 {
+                                       reg = <0x38 4>;
+                               };
+
+                               tempmon_temp_grade: temp-grade@20 {
+                                       reg = <0x20 4>;
+                               };
                        };
 
                        lcdif: lcdif@21c8000 {