drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR

This patches replaces the previously used static DDR vote and uses
dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
GPU frequency. Also since the icc path voting is handled completely
in the opp driver, remove the icc_path handle and its usage in the
drm driver.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index b67b38c8fadf73a6834acf77e2a0ae1baf8dc74d..5b2df7d4813866096fbe8f69d49f67cad14fdc5b 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -133,7 +133,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
 
        if (!gmu->legacy) {
                a6xx_hfi_set_freq(gmu, perf_index);
-               icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
+               dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
                pm_runtime_put(gmu->dev);
                return;
        }
@@ -157,11 +157,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
        if (ret)
                dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
-       /*
-        * Eventually we will want to scale the path vote with the frequency but
-        * for now leave it at max so that the performance is nominal.
-        */
-       icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
+       dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
        pm_runtime_put(gmu->dev);
 }
 
@@ -849,6 +845,19 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
        dev_pm_opp_put(gpu_opp);
 }
 
+static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
+{
+       struct dev_pm_opp *gpu_opp;
+       unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
+
+       gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
+       if (IS_ERR_OR_NULL(gpu_opp))
+               return;
+
+       dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp);
+       dev_pm_opp_put(gpu_opp);
+}
+
 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 {
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
@@ -882,7 +891,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
        }
 
        /* Set the bus quota to a reasonable value for boot */
-       icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072));
+       a6xx_gmu_set_initial_bw(gpu, gmu);
 
        /* Enable the GMU interrupt */
        gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
@@ -1051,7 +1060,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
                a6xx_gmu_shutdown(gmu);
 
        /* Remove the bus vote */
-       icc_set_bw(gpu->icc_path, 0, 0);
+       dev_pm_opp_set_bw(&gpu->pdev->dev, NULL);
 
        /*
         * Make sure the GX domain is off before turning off the GMU (CX)