clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary

CLK_GET_RATE_NOCACHE should only be necessary when the registers
controlling the rate of clock may change outside of CCF. On Amlogic,
it should only be the case for the hdmi pll which is directly controlled
by the display driver (WIP to fix this).

The other plls should not require this flag.

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 6d897655465664a9b807176d1f0457b7f0db90b0..991fa511c05a508cba58ee81f998d6e14c24341e 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -106,7 +106,6 @@ static struct clk_regmap axg_sys_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 5ed34566917cd780e5bddbba718ef938c29390ff..01e3f80e88cc51db8a6e6386aa2373c35cc29774 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -218,7 +218,6 @@ static struct clk_regmap gxbb_fixed_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 
@@ -286,6 +285,10 @@ static struct clk_regmap gxbb_hdmi_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
                .num_parents = 1,
+               /*
+                * Display directly handle hdmi pll registers ATM, we need
+                * NOCACHE to keep our view of the clock as accurate as possible
+                */
                .flags = CLK_GET_RATE_NOCACHE,
        },
 };
@@ -349,6 +352,10 @@ static struct clk_regmap gxl_hdmi_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
+               /*
+                * Display directly handle hdmi pll registers ATM, we need
+                * NOCACHE to keep our view of the clock as accurate as possible
+                */
                .flags = CLK_GET_RATE_NOCACHE,
        },
 };
@@ -391,7 +398,6 @@ static struct clk_regmap gxbb_sys_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 
@@ -442,7 +448,6 @@ static struct clk_regmap gxbb_gp0_pll = {
                .ops = &meson_clk_pll_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 
@@ -500,7 +505,6 @@ static struct clk_regmap gxl_gp0_pll = {
                .ops = &meson_clk_pll_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index fd4c414893f561a46388dd6e88bdb4cdda4a86a0..ec1f97725b9f6f074ffdd51389711b1fd8c85caa 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -137,7 +137,6 @@ static struct clk_regmap meson8b_fixed_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 
@@ -179,7 +178,6 @@ static struct clk_regmap meson8b_vid_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };
 
@@ -222,7 +220,6 @@ static struct clk_regmap meson8b_sys_pll = {
                .ops = &meson_clk_pll_ro_ops,
                .parent_names = (const char *[]){ "xtal" },
                .num_parents = 1,
-               .flags = CLK_GET_RATE_NOCACHE,
        },
 };