]> git.proxmox.com Git - mirror_qemu.git/commitdiff
target/m68k: Fix MACSR to CCR
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 13 Sep 2022 14:28:17 +0000 (15:28 +0100)
committerLaurent Vivier <laurent@vivier.eu>
Wed, 21 Sep 2022 13:01:37 +0000 (15:01 +0200)
First, we were writing to the entire SR register, instead
of only the flags portion.  Second, we were not clearing C
as per the documentation (X was cleared via the 0xf mask).

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
target/m68k/translate.c

index ffcc761d6011f78fd6f3eeb56e034391da32f5aa..c9bb05380323ed04c38b8e25b93ca47e147696c0 100644 (file)
@@ -5912,8 +5912,10 @@ DISAS_INSN(from_mext)
 DISAS_INSN(macsr_to_ccr)
 {
     TCGv tmp = tcg_temp_new();
-    tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
-    gen_helper_set_sr(cpu_env, tmp);
+
+    /* Note that X and C are always cleared. */
+    tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
+    gen_helper_set_ccr(cpu_env, tmp);
     tcg_temp_free(tmp);
     set_cc_op(s, CC_OP_FLAGS);
 }