mmio = qemu_mallocz(sizeof(subpage_t));
mmio->base = base;
- subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
+ subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio,
+ DEVICE_NATIVE_ENDIAN);
#if defined(DEBUG_SUBPAGE)
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
void *opaque, enum device_endian endian)
{
int i;
- int endian = DEVICE_NATIVE_ENDIAN;
if (io_index <= 0) {
io_index = get_free_io_mem_idx();
CPUWriteMemoryFunc * const *mem_write,
void *opaque, enum device_endian endian)
{
- return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
+ return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian);
}
void cpu_unregister_io_memory(int io_table_address)
{
int i;
- cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
- cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
- cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
+ cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read,
+ unassigned_mem_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read,
+ unassigned_mem_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read,
+ notdirty_mem_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
for (i=0; i<5; i++)
io_mem_used[i] = 1;
io_mem_watch = cpu_register_io_memory(watch_mem_read,
- watch_mem_write, NULL);
+ watch_mem_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
}
#endif /* !defined(CONFIG_USER_ONLY) */
/* apb_config */
apb_config = cpu_register_io_memory(apb_config_read,
- apb_config_write, s);
+ apb_config_write, s,
+ DEVICE_NATIVE_ENDIAN);
/* at region 0 */
sysbus_init_mmio(dev, 0x10000ULL, apb_config);
/* pci_ioport */
pci_ioport = cpu_register_io_memory(pci_apb_ioread,
- pci_apb_iowrite, s);
+ pci_apb_iowrite, s,
+ DEVICE_NATIVE_ENDIAN);
/* at region 2 */
sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
return -1;
}
apic_io_memory = cpu_register_io_memory(apic_mem_read,
- apic_mem_write, NULL);
+ apic_mem_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
- gic_dist_writefn, s);
+ gic_dist_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
}
int iomemtype;
iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
- arm_sysctl_writefn, s);
+ arm_sysctl_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* ??? Save/restore. */
return 0;
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
iomemtype = cpu_register_io_memory(sp804_readfn,
- sp804_writefn, s);
+ sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm(&dev->qdev, "sp804", -1, 1, sp804_save, sp804_load, s);
return 0;
sysbus_init_irq(dev, &s->timer[2]->irq);
iomemtype = cpu_register_io_memory(icp_pit_readfn,
- icp_pit_writefn, s);
+ icp_pit_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* This device has no state to save/restore. The component timers will
save themselves. */
int iomemtype;
iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
- &s->base);
+ &s->base, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x02000000, iomemtype);
return 0;
}
/* Attach a NAND flash to CS1. */
nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
- nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state);
+ nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
gpio_state.nand = &nand_state;
- gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state);
+ gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
pci_config_set_revision(dev->config, 0x01);
/* set the north bridge register mapping */
- s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s);
+ s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
+ DEVICE_NATIVE_ENDIAN);
s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
/* set the north bridge pci configure mapping */
s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
- bonito_pciconf_write, s);
+ bonito_pciconf_write, s,
+ DEVICE_NATIVE_ENDIAN);
s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
/* set the south bridge pci configure mapping */
s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
- bonito_spciconf_write, s);
+ bonito_spciconf_write, s,
+ DEVICE_NATIVE_ENDIAN);
s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
s->bonito_spciconf_handle);
s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
- bonito_ldma_write, s);
+ bonito_ldma_write, s,
+ DEVICE_NATIVE_ENDIAN);
s->bonito_ldma_start = 0xbfe00200;
s->bonito_ldma_length = 0x100;
cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
s->bonito_ldma_handle);
s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
- bonito_cop_write, s);
+ bonito_cop_write, s,
+ DEVICE_NATIVE_ENDIAN);
s->bonito_cop_start = 0xbfe00300;
s->bonito_cop_length = 0x100;
cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
- cirrus_vga_mem_write, s);
+ cirrus_vga_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
s->vga.vga_io_memory);
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
/* I/O handler for LFB */
s->cirrus_linear_io_addr =
- cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
+ cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s,
+ DEVICE_NATIVE_ENDIAN);
/* I/O handler for LFB */
s->cirrus_linear_bitblt_io_addr =
cpu_register_io_memory(cirrus_linear_bitblt_read,
- cirrus_linear_bitblt_write, s);
+ cirrus_linear_bitblt_write, s,
+ DEVICE_NATIVE_ENDIAN);
/* I/O handler for memory-mapped I/O */
s->cirrus_mmio_io_addr =
- cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
+ cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s,
+ DEVICE_NATIVE_ENDIAN);
s->real_vram_size =
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
int io;
CSState *s = FROM_SYSBUS(CSState, dev);
- io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
+ io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, CS_SIZE, io);
sysbus_init_irq(dev, &s->irq);
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
- *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
+ *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s,
+ DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, s);
}
qemu_register_reset(nic_reset, s);
nic_reset(s);
- s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
+ s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
}
}
/* Read/write memory */
- mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
+ mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
/* Read/write protected memory */
- mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
+ mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
return s;
}
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
- e1000_mmio_write, d);
+ e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
pci_register_bar(&d->dev, 0, PNPMMIO_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
sysbus_init_irq(dev, &s->irq);
s->regs[0] = s->version;
- ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
+ ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
if (s->version == ECC_MCC) { // SS-600MP only
ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
- ecc_diag_mem_write, s);
+ ecc_diag_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
}
/* Handler for memory-mapped I/O */
s->mmio_index =
- cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
+ cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
+ DEVICE_NATIVE_ENDIAN);
pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY |
ram_addr_t empty_slot_offset;
empty_slot_offset = cpu_register_io_memory(empty_slot_read,
- empty_slot_write, s);
+ empty_slot_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, empty_slot_offset | IO_MEM_RAM);
return 0;
}
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
- io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s);
+ io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io);
s->mmio_index = io;
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
- esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
+ esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
- ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl);
+ ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
return ctrl;
}
tdk_init(ð->phy);
mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr);
- eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth);
+ eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
memcpy(eth->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
- intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s);
+ intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs);
return 0;
}
s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
sysbus_init_irq(dev, &s->irq);
- ser_regs = cpu_register_io_memory(ser_read, ser_write, s);
+ ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr)
sysbus_init_irq(dev, &t->irq);
sysbus_init_irq(dev, &t->nmi);
- timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
+ timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, t);
int io;
int ret;
- io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
+ io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x08, io);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
- fdctrl_mem_write_strict, fdctrl);
+ fdctrl_mem_write_strict, fdctrl,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x08, io);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
int io_ctl_memory, io_data_memory;
io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
- fw_cfg_ctl_mem_write, s);
+ fw_cfg_ctl_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_ctl_memory);
io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
- fw_cfg_data_mem_write, s);
+ fw_cfg_data_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_data_memory);
if (s->ctl_iobase) {
cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
- io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s);
+ io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
return 0;
s->pci->bus = pci_register_bus(NULL, "pci",
pci_gt64120_set_irq, pci_gt64120_map_irq,
pic, PCI_DEVFN(18, 0), 4);
- s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
+ s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s,
+ DEVICE_NATIVE_ENDIAN);
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
0, NULL, NULL);
s = qemu_mallocz(sizeof(HeathrowPICS));
/* only 1 CPU */
s->irqs = irqs[0];
- *pmem_index = cpu_register_io_memory(pic_read, pic_write, s);
+ *pmem_index = cpu_register_io_memory(pic_read, pic_write, s,
+ DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);
/* HPET Area */
iomemtype = cpu_register_io_memory(hpet_ram_read,
- hpet_ram_write, s);
+ hpet_ram_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x400, iomemtype);
return 0;
}
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
- pmac_ide_write, d);
+ pmac_ide_write, d,
+ DEVICE_NATIVE_ENDIAN);
vmstate_register(NULL, 0, &vmstate_pmac, d);
qemu_register_reset(pmac_ide_reset, d);
s->shift = shift;
- mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
- mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
+ mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s,
+ DEVICE_NATIVE_ENDIAN);
+ mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(membase, 16 << shift, mem1);
cpu_register_physical_memory(membase2, 2 << shift, mem2);
vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
iomemtype = cpu_register_io_memory(integratorcm_readfn,
- integratorcm_writefn, s);
+ integratorcm_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
integratorcm_do_remap(s, 1);
/* ??? Save/restore. */
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
iomemtype = cpu_register_io_memory(icp_pic_readfn,
- icp_pic_writefn, s);
+ icp_pic_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
return 0;
}
int iomemtype;
iomemtype = cpu_register_io_memory(icp_control_readfn,
- icp_control_writefn, NULL);
+ icp_control_writefn, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
/* ??? Save/restore. */
}
conf[0x40] = 0x01;
d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
- intel_hda_mmio_write, d);
+ intel_hda_mmio_write, d,
+ DEVICE_NATIVE_ENDIAN);
pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY,
intel_hda_map);
if (d->msi) {
int io_memory;
io_memory = cpu_register_io_memory(ioapic_mem_read,
- ioapic_mem_write, s);
+ ioapic_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, io_memory);
qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
if (be) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,
isa_mmio_write_be,
- NULL);
+ NULL,
+ DEVICE_NATIVE_ENDIAN);
} else {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,
isa_mmio_write_le,
- NULL);
+ NULL,
+ DEVICE_NATIVE_ENDIAN);
}
}
cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
s->shm_fd = 0;
s->ivshmem_mmio_io_addr = cpu_register_io_memory(ivshmem_mmio_read,
- ivshmem_mmio_write, s);
+ ivshmem_mmio_write, s, DEVICE_NATIVE_ENDIAN);
/* region for registers*/
pci_register_bar(&s->dev, 0, IVSHMEM_REG_BAR_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_mmio_map);
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
- io = cpu_register_io_memory(led_read, led_write, s);
+ io = cpu_register_io_memory(led_read, led_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 1, io);
s->ds = graphic_console_init(jazz_led_update_display,
int i;
s->mmio_index = cpu_register_io_memory(lan9118_readfn,
- lan9118_writefn, s);
+ lan9118_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x100, s->mmio_index);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
PCNetState *s = &d->state;
s->mmio_index =
- cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
+ cpu_register_io_memory(lance_mem_read, lance_mem_write, d,
+ DEVICE_NATIVE_ENDIAN);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
pci_conf[PCI_INTERRUPT_PIN] = 0x01;
s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn,
- lsi_mmio_writefn, s);
+ lsi_mmio_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,
- lsi_ram_writefn, s);
+ lsi_ram_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
pci_register_bar(&s->dev, 0, 256,
PCI_BASE_ADDRESS_SPACE_IO, lsi_io_mapfunc);
sysbus_init_irq(dev, &s->IRQ);
- mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
+ mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, mem_index);
m48t59_init_common(s);
s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
- *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
+ *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s,
+ DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, s);
s->size = size;
s->it_shift = it_shift;
- s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
+ s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
+ DEVICE_NATIVE_ENDIAN);
*mem_index = s->mem_index;
register_savevm(NULL, "macio_nvram", -1, 1, macio_nvram_save,
macio_nvram_load, s);
wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s);
iomemtype = cpu_register_io_memory(mv88w8618_audio_readfn,
- mv88w8618_audio_writefn, s);
+ mv88w8618_audio_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_AUDIO_SIZE, iomemtype);
return 0;
s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));
iomemtype = cpu_register_io_memory(m5206_mbar_readfn,
- m5206_mbar_writefn, s);
+ m5206_mbar_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
int i;
iomemtype = cpu_register_io_memory(m5208_sys_readfn,
- m5208_sys_writefn, NULL);
+ m5208_sys_writefn, NULL,
+ DEVICE_NATIVE_ENDIAN);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
/* Timers. */
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
iomemtype = cpu_register_io_memory(m5208_timer_readfn,
- m5208_timer_writefn, s);
+ m5208_timer_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
s->irq = pic[4 + i];
s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state));
s->irq = irq;
s->mmio_index = cpu_register_io_memory(mcf_fec_readfn,
- mcf_fec_writefn, s);
+ mcf_fec_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x400, s->mmio_index);
memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
mcf_intc_reset(s);
iomemtype = cpu_register_io_memory(mcf_intc_readfn,
- mcf_intc_writefn, s);
+ mcf_intc_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
s = mcf_uart_init(irq, chr);
iomemtype = cpu_register_io_memory(mcf_uart_readfn,
- mcf_uart_writefn, s);
+ mcf_uart_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40, iomemtype);
}
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
- s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
+ s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
/* ISA devices */
/* Real time clock */
rtc_init(1980, NULL);
- s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
+ s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
/* Keyboard (i8042) */
s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
malta = cpu_register_io_memory(malta_fpga_read,
- malta_fpga_write, s);
+ malta_fpga_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x900, malta);
/* 0xa00 is less than a page, so will still get the right offsets. */
if (!mips_qemu_iomemtype) {
mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
- mips_qemu_write, NULL);
+ mips_qemu_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
}
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
gic_init(&s->gic, s->num_cpu);
s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
- mpcore_priv_writefn, s);
+ mpcore_priv_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i);
msix_mask_all(dev, nentries);
dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
- msix_mmio_write, dev);
+ msix_mmio_write, dev,
+ DEVICE_NATIVE_ENDIAN);
if (dev->msix_mmio_index == -1) {
ret = -EBUSY;
goto err_index;
s->pins = qi;
iomemtype = cpu_register_io_memory(mst_fpga_readfn,
- mst_fpga_writefn, s);
+ mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
mst_fpga_load, s);
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
- mv88w8618_eth_writefn, s);
+ mv88w8618_eth_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
return 0;
}
s->brightness = 7;
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
- musicpal_lcd_writefn, s);
+ musicpal_lcd_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
- mv88w8618_pic_writefn, s);
+ mv88w8618_pic_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
return 0;
}
}
iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
- mv88w8618_pit_writefn, s);
+ mv88w8618_pit_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
return 0;
}
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
- mv88w8618_flashcfg_writefn, s);
+ mv88w8618_flashcfg_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
return 0;
}
int iomemtype;
iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
- musicpal_misc_writefn, NULL);
+ musicpal_misc_writefn, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
}
int iomemtype;
iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
- mv88w8618_wlan_writefn, NULL);
+ mv88w8618_wlan_writefn, NULL,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
return 0;
}
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
- musicpal_gpio_writefn, s);
+ musicpal_gpio_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
s->mem_write = mem_write;
s->opaque = opaque;
s->in = 0;
- return cpu_register_io_memory(io_readfn, io_writefn, s);
+ return cpu_register_io_memory(io_readfn, io_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
}
# define cpu_register_io_memory debug_register_io_memory
# endif
omap_timer_clk_setup(s);
iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
- omap_mpu_timer_writefn, s);
+ omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
- omap_wd_timer_writefn, s);
+ omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
- omap_os_timer_writefn, s);
+ omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
- omap_ulpd_pm_writefn, mpu);
+ omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_ulpd_pm_reset(mpu);
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
- omap_pin_cfg_writefn, mpu);
+ omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_pin_cfg_reset(mpu);
static void omap_id_init(struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_id_readfn,
- omap_id_writefn, mpu);
+ omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
if (!cpu_is_omap15xx(mpu))
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
- omap_mpui_writefn, mpu);
+ omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
omap_tipb_bridge_reset(s);
iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
- omap_tipb_bridge_writefn, s);
+ omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
- omap_tcmi_writefn, mpu);
+ omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
omap_tcmi_reset(mpu);
omap_clk clk)
{
int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
- omap_dpll_writefn, s);
+ omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
s->dpll = clk;
omap_dpll_reset(s);
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
int iomemtype[2] = {
- cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
- cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s),
+ cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
+ DEVICE_NATIVE_ENDIAN),
+ cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
+ DEVICE_NATIVE_ENDIAN),
};
s->clkm.arm_idlect1 = 0x03ff;
omap_mpuio_reset(s);
iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
- omap_mpuio_writefn, s);
+ omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
omap_uwire_reset(s);
iomemtype = cpu_register_io_memory(omap_uwire_readfn,
- omap_uwire_writefn, s);
+ omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
omap_pwl_reset(s);
iomemtype = cpu_register_io_memory(omap_pwl_readfn,
- omap_pwl_writefn, s);
+ omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
omap_pwt_reset(s);
iomemtype = cpu_register_io_memory(omap_pwt_readfn,
- omap_pwt_writefn, s);
+ omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
}
omap_rtc_reset(s);
iomemtype = cpu_register_io_memory(omap_rtc_readfn,
- omap_rtc_writefn, s);
+ omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
omap_mcbsp_reset(s);
iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
- omap_mcbsp_writefn, s);
+ omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
omap_lpg_reset(s);
iomemtype = cpu_register_io_memory(omap_lpg_readfn,
- omap_lpg_writefn, s);
+ omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
- omap_mpui_io_writefn, mpu);
+ omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
}
AUD_register_card("OMAP EAC", &s->codec.card);
iomemtype = cpu_register_io_memory(omap_eac_readfn,
- omap_eac_writefn, s);
+ omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype);
return s;
omap_l4_attach(ta, 0, iomemtype);
iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
- omap_sti_fifo_writefn, s);
+ omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
return s;
omap_dma_clk_update(s, 0, 1);
iomemtype = cpu_register_io_memory(omap_dma_readfn,
- omap_dma_writefn, s);
+ omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, memsize, iomemtype);
mpu->drq = s->dma->drq;
omap_dma_clk_update(s, 0, !!s->dma->freq);
iomemtype = cpu_register_io_memory(omap_dma4_readfn,
- omap_dma4_writefn, s);
+ omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
mpu->drq = s->dma->drq;
iomemtype[3] = l4_register_io_memory(omap_venc1_readfn,
omap_venc1_writefn, s);
iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
- omap_im3_writefn, s);
+ omap_im3_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype[0]);
omap_l4_attach(ta, 1, iomemtype[1]);
omap_l4_attach(ta, 2, iomemtype[2]);
omap_gpio_reset(s);
iomemtype = cpu_register_io_memory(omap_gpio_readfn,
- omap_gpio_writefn, s);
+ omap_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;
omap_gpmc_reset(s);
iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s);
+ omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;
omap_i2c_reset(s);
iomemtype = cpu_register_io_memory(omap_i2c_readfn,
- omap_i2c_writefn, s);
+ omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
omap_inth_reset(s);
iomemtype = cpu_register_io_memory(omap_inth_readfn,
- omap_inth_writefn, s);
+ omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, size, iomemtype);
return s;
omap_inth_reset(s);
iomemtype = cpu_register_io_memory(omap2_inth_readfn,
- omap2_inth_writefn, s);
+ omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, size, iomemtype);
return s;
CPUWriteMemoryFunc * const *mem_write,
void *opaque)
{
- return cpu_register_io_memory(mem_read, mem_write, opaque);
+ return cpu_register_io_memory(mem_read, mem_write, opaque,
+ DEVICE_NATIVE_ENDIAN);
}
#endif
omap_cpu_io_entry =
cpu_register_io_memory(omap_l4_io_readfn,
- omap_l4_io_writefn, bus);
+ omap_l4_io_writefn, bus, DEVICE_NATIVE_ENDIAN);
# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
- omap_lcdc_writefn, s);
+ omap_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
s->state = graphic_console_init(omap_update_display,
omap_mmc_reset(s);
iomemtype = cpu_register_io_memory(omap_mmc_readfn,
- omap_mmc_writefn, s);
+ omap_mmc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
/* Instantiate the storage */
omap_sdrc_reset(s);
iomemtype = cpu_register_io_memory(omap_sdrc_readfn,
- omap_sdrc_writefn, s);
+ omap_sdrc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;
qemu_ram_alloc(NULL, "omap_sx1.flash0-0",
flash_size) | IO_MEM_ROM);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
fl_idx = 0;
cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
qemu_ram_alloc(NULL, "omap_sx1.flash1-0",
flash1_size) | IO_MEM_ROM);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io);
}
fl_idx++;
} else {
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
}
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
- omap_uart_writefn, s);
+ omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
s->ta = ta;
s->blockwp = qemu_malloc(s->blocks);
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(onenand_readfn,
- onenand_writefn, s);
+ onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
if (!dinfo)
s->image = memset(qemu_malloc(size + (size >> 5)),
0xff, size + (size >> 5));
cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(openpic_src_read,
- openpic_src_write);
+ openpic_src_write, NULL
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
#endif
} else {
opp = qemu_mallocz(sizeof(openpic_t));
}
- opp->mem_index = cpu_register_io_memory(openpic_read,
- openpic_write, opp);
+ opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
+ DEVICE_NATIVE_ENDIAN);
// isu_base &= 0xFFFC0000;
opp->nb_cpus = nb_cpus;
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;
- mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp);
+ mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
+ DEVICE_NATIVE_ENDIAN);
if (mem_index < 0) {
goto free;
}
qemu_ram_alloc(NULL, "palmte.flash",
flash_size) | IO_MEM_ROM);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
- io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
+ io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
palmte_microwire_setup(cpu);
s->it_shift = it_shift;
qemu_register_reset(parallel_reset, s);
- io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
+ io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw,
+ s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
return s;
}
{
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
e->mmio_index =
- cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e);
+ cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
+ DEVICE_NATIVE_ENDIAN);
if (e->mmio_index < 0) {
return -1;
}
s->mask = mask;
vmstate_register(NULL, 0, &vmstate_kbd, s);
- s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
+ s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, size, s_io_memory);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
/* Handler for memory-mapped I/O */
s->mmio_index =
- cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state);
+ cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state,
+ DEVICE_NATIVE_ENDIAN);
pci_register_bar(pci_dev, 0, PCNET_IOPORT_SIZE,
PCI_BASE_ADDRESS_SPACE_IO, pcnet_ioport_map);
pfl->storage = qemu_get_ram_ptr(off);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
- pflash_write_ops_be, pfl);
+ pflash_write_ops_be, pfl,
+ DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
- pflash_write_ops_le, pfl);
+ pflash_write_ops_le, pfl,
+ DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
cpu_register_physical_memory(base, total_len,
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be,
- pfl);
+ pfl, DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le,
- pfl);
+ pfl, DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
pfl->base = base;
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
iomemtype = cpu_register_io_memory(pl011_readfn,
- pl011_writefn, s);
+ pl011_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000,iomemtype);
sysbus_init_irq(dev, &s->irq);
s->id = id;
int iomemtype;
iomemtype = cpu_register_io_memory(pl022_readfn,
- pl022_writefn, s);
+ pl022_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->ssi = ssi_create_bus(&dev->qdev, "ssi");
pl031_state *s = FROM_SYSBUS(pl031_state, dev);
struct tm tm;
- iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s);
+ iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
if (iomemtype == -1) {
hw_error("pl031_init: Can't register I/O memory\n");
}
int iomemtype;
iomemtype = cpu_register_io_memory(pl050_readfn,
- pl050_writefn, s);
+ pl050_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->is_mouse = is_mouse;
pl061_state *s = FROM_SYSBUS(pl061_state, dev);
iomemtype = cpu_register_io_memory(pl061_readfn,
- pl061_writefn, s);
+ pl061_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
iomemtype = cpu_register_io_memory(pl080_readfn,
- pl080_writefn, s);
+ pl080_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->nchannels = nchannels;
int iomemtype;
iomemtype = cpu_register_io_memory(pl110_readfn,
- pl110_writefn, s);
+ pl110_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->ds = graphic_console_init(pl110_update_display,
pl181_state *s = FROM_SYSBUS(pl181_state, dev);
BlockDriverState *bd;
- iomemtype = cpu_register_io_memory(pl181_readfn,
- pl181_writefn, s);
+ iomemtype = cpu_register_io_memory(pl181_readfn, pl181_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq[0]);
sysbus_init_irq(dev, &s->irq[1]);
int iomemtype;
iomemtype = cpu_register_io_memory(pl190_readfn,
- pl190_writefn, s);
+ pl190_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
sysbus_init_irq(dev, &s->irq);
fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
- ref405ep_fpga_write, fpga);
+ ref405ep_fpga_write, fpga,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
cpld = qemu_mallocz(sizeof(taihu_cpld_t));
cpld_memory = cpu_register_io_memory(taihu_cpld_read,
- taihu_cpld_write, cpld);
+ taihu_cpld_write, cpld,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
qemu_register_reset(&taihu_cpld_reset, cpld);
}
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(opba_read, opba_write, opba);
+ io = cpu_register_io_memory(opba_read, opba_write, opba,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x002, io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
+ io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x038, io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
+ io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x011, io);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
+ io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x0d4, io);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
/* CFGADDR */
index = cpu_register_io_memory(pci4xx_cfgaddr_read,
- pci4xx_cfgaddr_write, controller);
+ pci4xx_cfgaddr_write, controller,
+ DEVICE_NATIVE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
/* Internal registers */
- index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
+ index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
+ DEVICE_NATIVE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
isa_mmio_init(0xf2000000, 0x00800000, 1);
/* UniN init */
- unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL);
+ unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
// pci_bus = i440fx_init();
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
- PPC_prep_io_write, sysctrl);
+ PPC_prep_io_write, sysctrl,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
/* init basic PC hardware */
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
/* PCI intack location */
PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
- PPC_intack_write, NULL);
+ PPC_intack_write, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
/* PowerPC control and status register group */
#if 0
PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
- NULL);
+ NULL, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
#endif
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
index = cpu_register_io_memory(e500_pci_reg_read,
- e500_pci_reg_write, controller);
+ e500_pci_reg_write, controller,
+ DEVICE_NATIVE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_REG_BASE,
pci_host_data_register_ioport(0xcfc, s);
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
- PPC_PCIIO_write, s);
+ PPC_PCIIO_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
/* PCI host bridge */
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
- pxa2xx_ssp_writefn, s);
+ pxa2xx_ssp_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
- pxa2xx_i2c_writefn, s);
+ pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base & ~region_size,
region_size + 1, iomemtype);
pxa2xx_i2s_reset(s);
iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
- pxa2xx_i2s_writefn, s);
+ pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100000, iomemtype);
register_savevm(NULL, "pxa2xx_i2s", base, 0,
pxa2xx_fir_reset(s);
iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
- pxa2xx_fir_writefn, s);
+ pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
if (chr)
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
- pxa2xx_cm_writefn, s);
+ pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
- pxa2xx_mm_writefn, s);
+ pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
- pxa2xx_pm_writefn, s);
+ pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
- pxa2xx_rtc_writefn, s);
+ pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
- pxa2xx_cm_writefn, s);
+ pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
- pxa2xx_mm_writefn, s);
+ pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
- pxa2xx_pm_writefn, s);
+ pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
- pxa2xx_rtc_writefn, s);
+ pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
- pxa2xx_dma_writefn, s);
+ pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00010000, iomemtype);
register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);
s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
- pxa2xx_gpio_writefn, s);
+ pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
register_savevm(NULL, "pxa2xx_gpio", 0, 0,
s->irq = irq;
iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn,
- pxa2xx_keypad_writefn, s);
+ pxa2xx_keypad_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm(NULL, "pxa2xx_keypad", 0, 0,
pxa2xx_lcdc_orientation(s, graphic_rotate);
iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
- pxa2xx_lcdc_writefn, s);
+ pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
s->ds = graphic_console_init(pxa2xx_update_display,
s->dma = dma;
iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn,
- pxa2xx_mmci_writefn, s);
+ pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
/* Instantiate the actual storage */
/* Socket I/O Memory Space */
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
- pxa2xx_pcmcia_io_writefn, s);
+ pxa2xx_pcmcia_io_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
/* Then next 64 MB is reserved */
/* Socket Attribute Memory Space */
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
- pxa2xx_pcmcia_attr_writefn, s);
+ pxa2xx_pcmcia_attr_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
/* Socket Common Memory Space */
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
- pxa2xx_pcmcia_common_writefn, s);
+ pxa2xx_pcmcia_common_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
if (base == 0x30000000)
/* Enable IC memory-mapped registers access. */
iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
- pxa2xx_pic_writefn, s);
+ pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
/* Enable IC coprocessor access. */
}
iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
- pxa2xx_timer_writefn, s);
+ pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
register_savevm(NULL, "pxa2xx_timer", 0, 0,
s->irl = irl;
iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
- r2d_fpga_writefn, s);
+ r2d_fpga_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40, iomemtype);
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}
register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
rc4030_reset(s);
- s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
+ s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
- s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s);
+ s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
return s;
bus = i2c_init_bus(&dev->qdev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
iomemtype = cpu_register_io_memory(realview_i2c_readfn,
- realview_i2c_writefn, s);
+ realview_i2c_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
return 0;
}
gic_init(&s->gic);
s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
- realview_gic_cpu_writefn, s);
+ realview_gic_cpu_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
return 0;
}
/* I/O handler for memory-mapped I/O */
s->rtl8139_mmio_io_addr =
- cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s);
+ cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
+ DEVICE_NATIVE_ENDIAN);
pci_register_bar(&s->dev, 0, 0x100,
PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
- sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
+ sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory);
return 0;
if (ioregister) {
if (be) {
s_io_memory = cpu_register_io_memory(serial_mm_read_be,
- serial_mm_write_be, s);
+ serial_mm_write_be, s,
+ DEVICE_NATIVE_ENDIAN);
} else {
s_io_memory = cpu_register_io_memory(serial_mm_read_le,
- serial_mm_write_le, s);
+ serial_mm_write_le, s,
+ DEVICE_NATIVE_ENDIAN);
}
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
}
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
- sh7750_mem_write, s);
+ sh7750_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory_offset(0x1f000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0xff000000, 0x1000,
sh7750_io_memory, 0x1fc00000);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
- sh7750_mmct_write, s);
+ sh7750_mmct_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xf0000000, 0x08000000,
sh7750_mm_cache_and_tlb);
desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
desc->iomemtype = cpu_register_io_memory(sh_intc_readfn,
- sh_intc_writefn, desc);
+ sh_intc_writefn, desc,
+ DEVICE_NATIVE_ENDIAN);
if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i;
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
-1, NULL, NULL);
- reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p);
+ reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x1e200000, 0x224, reg);
cpu_register_physical_memory(0xfe200000, 0x224, reg);
sh_serial_clear_fifo(s);
s_io_memory = cpu_register_io_memory(sh_serial_readfn,
- sh_serial_writefn, s);
+ sh_serial_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
ch2_irq0); /* ch2_irq1 not supported */
iomemtype = cpu_register_io_memory(tmu012_readfn,
- tmu012_writefn, s);
+ tmu012_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
/* ??? Save/restore. */
qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
- slavio_intctlm_mem_write, s);
+ slavio_intctlm_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
for (i = 0; i < MAX_CPUS; i++) {
}
io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
slavio_intctl_mem_write,
- &s->slaves[i]);
+ &s->slaves[i],
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
s->slaves[i].cpu = i;
s->slaves[i].master = s;
sysbus_init_irq(dev, &s->cpu_halt);
/* Power management (APC) XXX: not a Slavio device */
- io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
+ io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
return 0;
}
/* 8 bit registers */
/* Slavio control */
io = cpu_register_io_memory(slavio_cfg_mem_read,
- slavio_cfg_mem_write, s);
+ slavio_cfg_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* Diagnostics */
io = cpu_register_io_memory(slavio_diag_mem_read,
- slavio_diag_mem_write, s);
+ slavio_diag_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* Modem control */
io = cpu_register_io_memory(slavio_mdm_mem_read,
- slavio_mdm_mem_write, s);
+ slavio_mdm_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* 16 bit registers */
/* ss600mp diag LEDs */
io = cpu_register_io_memory(slavio_led_mem_read,
- slavio_led_mem_write, s);
+ slavio_led_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* 32 bit registers */
/* System control */
io = cpu_register_io_memory(slavio_sysctrl_mem_read,
- slavio_sysctrl_mem_write, s);
+ slavio_sysctrl_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
/* AUX 1 (Misc System Functions) */
io = cpu_register_io_memory(slavio_aux1_mem_read,
- slavio_aux1_mem_write, s);
+ slavio_aux1_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* AUX 2 (Software Powerdown Control) */
io = cpu_register_io_memory(slavio_aux2_mem_read,
- slavio_aux2_mem_write, s);
+ slavio_aux2_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
io = cpu_register_io_memory(slavio_timer_mem_read,
- slavio_timer_mem_write, tc);
+ slavio_timer_mem_write, tc,
+ DEVICE_NATIVE_ENDIAN);
if (i == 0) {
sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
} else {
/* map mmio */
sm501_system_config_index
= cpu_register_io_memory(sm501_system_config_readfn,
- sm501_system_config_writefn, s);
+ sm501_system_config_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
0x6c, sm501_system_config_index);
sm501_disp_ctrl_index = cpu_register_io_memory(sm501_disp_ctrl_readfn,
- sm501_disp_ctrl_writefn, s);
+ sm501_disp_ctrl_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
0x1000, sm501_disp_ctrl_index);
sm501_2d_engine_index = cpu_register_io_memory(sm501_2d_engine_readfn,
- sm501_2d_engine_writefn, s);
+ sm501_2d_engine_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
0x54, sm501_2d_engine_index);
smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev);
s->mmio_index = cpu_register_io_memory(smc91c111_readfn,
- smc91c111_writefn, s);
+ smc91c111_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 16, s->mmio_index);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
sysbus_init_irq(dev, &s->irq);
- dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
+ dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
iomemtype = cpu_register_io_memory(sl_readfn,
- sl_writefn, s);
+ sl_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
register_savevm(NULL, "sl_flash", 0, 0, sl_save, sl_load, s);
qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
iomemtype = cpu_register_io_memory(gptm_readfn,
- gptm_writefn, s);
+ gptm_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
s->opaque[0] = s->opaque[1] = s;
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
iomemtype = cpu_register_io_memory(ssys_readfn,
- ssys_writefn, s);
+ ssys_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
ssys_reset(s);
register_savevm(NULL, "stellaris_sys", -1, 1, ssys_save, ssys_load, s);
s->bus = bus;
iomemtype = cpu_register_io_memory(stellaris_i2c_readfn,
- stellaris_i2c_writefn, s);
+ stellaris_i2c_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* ??? For now we only implement the master interface. */
stellaris_i2c_reset(s);
}
iomemtype = cpu_register_io_memory(stellaris_adc_readfn,
- stellaris_adc_writefn, s);
+ stellaris_adc_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
stellaris_adc_reset(s);
qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
- stellaris_enet_writefn, s);
+ stellaris_enet_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, s->mmio_index);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
unsigned int i;
io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
- sun4c_intctl_mem_write, s);
+ sun4c_intctl_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
sysbus_init_irq(dev, &s->irq);
- io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
+ io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
return 0;
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(syborg_fb_readfn,
- syborg_fb_writefn, s);
+ syborg_fb_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
s->ds = graphic_console_init(syborg_fb_update_display,
sysbus_init_irq(dev, &s->parent_irq);
qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs);
iomemtype = cpu_register_io_memory(syborg_int_readfn,
- syborg_int_writefn, s);
+ syborg_int_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
s->flags = qemu_mallocz(s->num_irqs * sizeof(syborg_int_flags));
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(syborg_keyboard_readfn,
- syborg_keyboard_writefn, s);
+ syborg_keyboard_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
if (s->fifo_size <= 0) {
fprintf(stderr, "syborg_keyboard: fifo too small\n");
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(syborg_pointer_readfn,
- syborg_pointer_writefn, s);
+ syborg_pointer_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
if (s->fifo_size <= 0) {
int iomemtype;
iomemtype = cpu_register_io_memory(syborg_rtc_readfn,
- syborg_rtc_writefn, s);
+ syborg_rtc_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
qemu_get_timedate(&tm, 0);
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(syborg_serial_readfn,
- syborg_serial_writefn, s);
+ syborg_serial_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr) {
}
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(syborg_timer_readfn,
- syborg_timer_writefn, s);
+ syborg_timer_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
bh = qemu_bh_new(syborg_timer_tick, s);
proxy->vdev->nvectors = 0;
sysbus_init_irq(&proxy->busdev, &proxy->irq);
iomemtype = cpu_register_io_memory(syborg_virtio_readfn,
- syborg_virtio_writefn, proxy);
+ syborg_virtio_writefn, proxy,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(&proxy->busdev, 0x1000, iomemtype);
proxy->id = ((uint32_t)0x1af4 << 16) | vdev->device_id;
s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
iomemtype = cpu_register_io_memory(tc6393xb_readfn,
- tc6393xb_writefn, s);
+ tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x10000, iomemtype);
s->vram_addr = qemu_ram_alloc(NULL, "tc6393xb.vram", 0x100000);
vram_base += size;
/* DAC */
- io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s);
+ io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory);
/* TEC (dummy) */
dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write,
- s);
+ s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory);
/* THC: NetBSD writes here even with 8-bit display: dummy */
sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory);
s->intr = 0x00000000;
s->otg_timer_val = 0;
s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s);
+ tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
s->irq = intr;
s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s);
usb_frame_time, usb_bit_time);
}
- ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci);
+ ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
+ DEVICE_NATIVE_ENDIAN);
ohci->localmem_base = localmem_base;
ohci->name = dev->info->name;
/* ??? Register memory space. */
s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
- pci_vpb_config_write, bus);
+ pci_vpb_config_write, bus,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
pci_create_simple(bus, -1, "versatile_pci_host");
}
s->irq = 31;
iomemtype = cpu_register_io_memory(vpb_sic_readfn,
- vpb_sic_writefn, s);
+ vpb_sic_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* ??? Save/restore. */
return 0;
int s_ioport_ctrl, vga_io_memory;
s->it_shift = it_shift;
- s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);
- vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
+ s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s,
+ DEVICE_NATIVE_ENDIAN);
+ vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
vmstate_register(NULL, 0, &vmstate_vga_common, s);
#endif
#endif /* CONFIG_BOCHS_VBE */
- vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
+ vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
vga_io_memory);
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
s->vram_base = addr;
#ifdef DIRECT_VRAM
iomemtype = cpu_register_io_memory(vmsvga_vram_read,
- vmsvga_vram_write, s);
+ vmsvga_vram_write, s, DEVICE_NATIVE_ENDIAN);
#else
iomemtype = s->vga.vram_offset | IO_MEM_RAM;
#endif
i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n",
addr, size, type);
- io_mem = cpu_register_io_memory(mem_read, mem_write, d);
+ io_mem = cpu_register_io_memory(mem_read, mem_write, d,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory (addr, 0x10, io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
}
sysbus_init_irq(dev, &s->irq);
s->rxbuf = 0;
- regs = cpu_register_io_memory(eth_read, eth_write, s);
+ regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, regs);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &p->parent_irq);
- pic_regs = cpu_register_io_memory(pic_read, pic_write, p);
+ pic_regs = cpu_register_io_memory(pic_read, pic_write, p, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, pic_regs);
return 0;
}
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
- timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
+ timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
return 0;
}
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
- uart_regs = cpu_register_io_memory(uart_read, uart_write, s);
+ uart_regs = cpu_register_io_memory(uart_read, uart_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
s->chr = qdev_init_chardev(&dev->qdev);
s->status = 0x02;
s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
iomemtype = cpu_register_io_memory(scoop_readfn,
- scoop_writefn, s);
+ scoop_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(target_base, 0x1000, iomemtype);
register_savevm(NULL, "scoop", instance, 1, scoop_save, scoop_load, s);
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
- handler);
+ handler, DEVICE_NATIVE_ENDIAN);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
projects / qemu.git / commitdiff