ASoC: ti: davinci-mcasp: Improve the sysclk selection

When McASP is master the bclk can be generated from two main source:
AUXCLK: functional clock for McASP or
AHCLK: from external source or internal mux in dra7x family

With this patch it is possible to select between the two source. The patch
is not breaking existing machine drivers since historically the clk_id was
ignored and left as 0 in all cases.

When output clock is configured - which can be only the AHCLK, we select
the AUXCLK as source for the internal HCLK. In this case the HCLK rate is
the same as the output clock.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Link: https://lore.kernel.org/r/20191204192005.31210-1-peter.ujfalusi@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c
index 8e5371801d88d22203af71cf23bf514bb88b8e09..e1e937eb1dc1acca46e63a0e42ac2f6e792a17ae 100644 (file)
--- a/sound/soc/ti/davinci-mcasp.c
+++ b/sound/soc/ti/davinci-mcasp.c
@@ -664,18 +664,39 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
        struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
 
        pm_runtime_get_sync(mcasp->dev);
-       if (dir == SND_SOC_CLOCK_OUT) {
+
+       if (dir == SND_SOC_CLOCK_IN) {
+               switch (clk_id) {
+               case MCASP_CLK_HCLK_AHCLK:
+                       mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+                                      AHCLKXE);
+                       mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+                                      AHCLKRE);
+                       clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+                       break;
+               case MCASP_CLK_HCLK_AUXCLK:
+                       mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
+                                      AHCLKXE);
+                       mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
+                                      AHCLKRE);
+                       set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
+                       break;
+               default:
+                       dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
+                       goto out;
+               }
+       } else {
+               /* Select AUXCLK as HCLK */
                mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
                mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
                set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
-       } else {
-               mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
-               mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
-               clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
        }
-
+       /*
+        * When AHCLK X/R is selected to be output it means that the HCLK is
+        * the same clock - coming via AUXCLK.
+        */
        mcasp->sysclk_freq = freq;
-
+out:
        pm_runtime_put(mcasp->dev);
        return 0;
 }

diff --git a/sound/soc/ti/davinci-mcasp.h b/sound/soc/ti/davinci-mcasp.h
index bc705d6ca48b11fb9ce55544f980dd315a276f89..5de2b8a31061c9f732fc56befd32f597244d3e16 100644 (file)
--- a/sound/soc/ti/davinci-mcasp.h
+++ b/sound/soc/ti/davinci-mcasp.h
@@ -295,6 +295,10 @@
 #define NUMEVT(x)      (((x) & 0xFF) << 8)
 #define NUMDMA_MASK    (0xFF)
 
+/* Source of High-frequency transmit/receive clock */
+#define MCASP_CLK_HCLK_AHCLK           0 /* AHCLKX/R */
+#define MCASP_CLK_HCLK_AUXCLK          1 /* Internal functional clock */
+
 /* clock divider IDs */
 #define MCASP_CLKDIV_AUXCLK            0 /* HCLK divider from AUXCLK */
 #define MCASP_CLKDIV_BCLK              1 /* BCLK divider from HCLK */