drm/amd/display: Calculate DSC number of slices in debugfs when forced

[why]
When comparing current DSC timing settings with enforced through
debugfs we have to calculate number of both vertical and horisontal
slices. So instead of doing that every time we should just
use number of slices rather than setting its dimensions.

[how]
In connector's dsc preferred settings structure change slice height
and slice width parameters to number of slices vertical and horisontal.
Also calculate number of slices in debugfs rather in create_stream_for_sink.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4684820e4dc8dcc3b838c00955325ec682167e5a..13ac3bf8ee9d2aa0491ea885d1e3eefef2c7bd25 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4701,13 +4701,11 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                        if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
                                stream->timing.flags.DSC = 1;
 
-                       if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_slice_width)
-                               stream->timing.dsc_cfg.num_slices_h = DIV_ROUND_UP(stream->timing.h_addressable,
-                                                                       aconnector->dsc_settings.dsc_slice_width);
+                       if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
+                               stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
 
-                       if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_slice_height)
-                               stream->timing.dsc_cfg.num_slices_v = DIV_ROUND_UP(stream->timing.v_addressable,
-                                                                       aconnector->dsc_settings.dsc_slice_height);
+                       if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
+                               stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
 
                        if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
                                stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ec8bd5fc8776cb5a550f06d9e16551fb8a368300..9c1e003d9c29553579bf008eebf465fc69c50c7a 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -351,8 +351,8 @@ enum dsc_clock_force_state {
 
 struct dsc_preferred_settings {
        enum dsc_clock_force_state dsc_force_enable;
-       uint32_t dsc_slice_width;
-       uint32_t dsc_slice_height;
+       uint32_t dsc_num_slices_v;
+       uint32_t dsc_num_slices_h;
        uint32_t dsc_bits_per_pixel;
 };
 

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 240a4fc403df82b00fbdc58d36908ac025dbd4f8..9be2f291382df9b55f7ce4df19d3cbcb7cd929ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1447,7 +1447,12 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
        if (!pipe_ctx || !pipe_ctx->stream)
                goto done;
 
-       aconnector->dsc_settings.dsc_slice_width = param[0];
+       if (param[0] > 0)
+               aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
+                                       pipe_ctx->stream->timing.h_addressable,
+                                       param[0]);
+       else
+               aconnector->dsc_settings.dsc_num_slices_h = 0;
 
 done:
        kfree(wr_buf);
@@ -1596,7 +1601,12 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
        if (!pipe_ctx || !pipe_ctx->stream)
                goto done;
 
-       aconnector->dsc_settings.dsc_slice_height = param[0];
+       if (param[0] > 0)
+               aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
+                                       pipe_ctx->stream->timing.v_addressable,
+                                       param[0]);
+       else
+               aconnector->dsc_settings.dsc_num_slices_v = 0;
 
 done:
        kfree(wr_buf);

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 14c04c1ac9bb30e0ebd06c562f38c54bde00c727..9d7333a36facfa34b656b8a367d28ac16a1418a1 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -454,8 +454,8 @@ struct dsc_mst_fairness_params {
        bool compression_possible;
        struct drm_dp_mst_port *port;
        enum dsc_clock_force_state clock_force_enable;
-       uint32_t slice_width_overwrite;
-       uint32_t slice_height_overwrite;
+       uint32_t num_slices_h;
+       uint32_t num_slices_v;
        uint32_t bpp_overwrite;
 };
 
@@ -496,15 +496,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
                        else
                                params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 
-                       if (params[i].slice_width_overwrite)
-                               params[i].timing->dsc_cfg.num_slices_h = DIV_ROUND_UP(
-                                                                               params[i].timing->h_addressable,
-                                                                               params[i].slice_width_overwrite);
+                       if (params[i].num_slices_h)
+                               params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
 
-                       if (params[i].slice_height_overwrite)
-                               params[i].timing->dsc_cfg.num_slices_v = DIV_ROUND_UP(
-                                                                               params[i].timing->v_addressable,
-                                                                               params[i].slice_height_overwrite);
+                       if (params[i].num_slices_v)
+                               params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
                } else {
                        params[i].timing->flags.DSC = 0;
                }
@@ -721,8 +717,8 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
                params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
                if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
                        debugfs_overwrite = true;
-               params[count].slice_width_overwrite = aconnector->dsc_settings.dsc_slice_width;
-               params[count].slice_height_overwrite = aconnector->dsc_settings.dsc_slice_height;
+               params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
+               params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
                params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
                params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
                dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);