MIPS: PCI: remember nasid changed by set interrupt affinity

BugLink: https://bugs.launchpad.net/bugs/1862227
commit 37640adbefd66491cb8083a438f7bf366ac09bc7 upstream.

When changing interrupt affinity remember the possible changed nasid,
otherwise an interrupt deactivate/activate sequence will incorrectly
setup interrupt.

Fixes: e6308b6d35ea ("MIPS: SGI-IP27: abstract chipset irq from bridge")
Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/mips/pci/pci-xtalk-bridge.c b/arch/mips/pci/pci-xtalk-bridge.c
index bcf7f559789a0295b08bd11c20d6957b68e6c1a4..0882fcfce02d8d9fffc34b5d9329d32299ab4a3c 100644 (file)
--- a/arch/mips/pci/pci-xtalk-bridge.c
+++ b/arch/mips/pci/pci-xtalk-bridge.c
@@ -322,16 +322,15 @@ static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
        struct bridge_irq_chip_data *data = d->chip_data;
        int bit = d->parent_data->hwirq;
        int pin = d->hwirq;
-       nasid_t nasid;
        int ret, cpu;
 
        ret = irq_chip_set_affinity_parent(d, mask, force);
        if (ret >= 0) {
                cpu = cpumask_first_and(mask, cpu_online_mask);
-               nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
+               data->nnasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
                bridge_write(data->bc, b_int_addr[pin].addr,
                             (((data->bc->intr_addr >> 30) & 0x30000) |
-                             bit | (nasid << 8)));
+                             bit | (data->nasid << 8)));
                bridge_read(data->bc, b_wid_tflush);
        }
        return ret;