ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect

BugLink: https://bugs.launchpad.net/bugs/1863019
[ Upstream commit c7861adbe37f576931650ad8ef805e0c47564b9a ]

Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
are pointing towards the same internal PCS. Therefore nobody is
controlling the internal PCS of eTSEC0.

Upon initial ndo_open, the SGMII link is ok by virtue of U-boot
initialization. But upon an ifdown/ifup sequence, the code path from
ndo_open -> init_phy -> gfar_configure_serdes does not get executed for
the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII
link remains down for eTSEC0. On the LS1021A-TWR board, to signal this
failure condition, the PHY driver keeps printing
'803x_aneg_done: SGMII link is not ok'.

Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match
mdio1 device.

Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 44715c8ef756b9f44bdc7a7c69b0cdc12c26d93d..72a3fc63d0ece95bcd41ab26d85199678ea4f6e7 100644 (file)
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -143,7 +143,7 @@
 };
 
 &enet0 {
-       tbi-handle = <&tbi1>;
+       tbi-handle = <&tbi0>;
        phy-handle = <&sgmii_phy2>;
        phy-connection-type = "sgmii";
        status = "okay";
@@ -222,6 +222,13 @@
        sgmii_phy2: ethernet-phy@2 {
                reg = <0x2>;
        };
+       tbi0: tbi-phy@1f {
+               reg = <0x1f>;
+               device_type = "tbi-phy";
+       };
+};
+
+&mdio1 {
        tbi1: tbi-phy@1f {
                reg = <0x1f>;
                device_type = "tbi-phy";

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2d20f60947b951bd1181cef7326a76f82213f45c..1343c86988c54d2653bb39bc9e3ca2cf7629f69e 100644 (file)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -562,13 +562,22 @@
                };
 
                mdio0: mdio@2d24000 {
-                       compatible = "gianfar";
+                       compatible = "fsl,etsec2-mdio";
                        device_type = "mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x0 0x2d24000 0x0 0x4000>;
                };
 
+               mdio1: mdio@2d64000 {
+                       compatible = "fsl,etsec2-mdio";
+                       device_type = "mdio";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2d64000 0x0 0x4000>,
+                             <0x0 0x2d50030 0x0 0x4>;
+               };
+
                ptp_clock@2d10e00 {
                        compatible = "fsl,etsec-ptp";
                        reg = <0x0 0x2d10e00 0x0 0xb0>;