#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
+#endif
#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_VANGOGH:
#endif
fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
break;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+ dmub_asic = DMUB_ASIC_DCN302;
+ fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
+ break;
+#endif
default:
/* ASIC doesn't support DMUB. */
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_VANGOGH:
#endif
break;
#endif
case CHIP_NAVI14:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+#endif
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER ||
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
+#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
adev->asic_type == CHIP_VANGOGH ||
#endif
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_DIMGREY_CAVEFISH)
tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
#endif
ret = fill_plane_dcc_attributes(adev, afb, format, rotation,