cpu_model = "m5206";
env = cpu_init(cpu_model);
if (!env) {
- cpu_abort(env, "Unable to find m68k CPU definition\n");
+ hw_error("Unable to find m68k CPU definition\n");
}
/* Initialize CPU registers. */
}
return res;
bad_reg:
- cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset);
+ hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
return 0;
}
gic_update(s);
return;
bad_reg:
- cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset);
+ hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
case 0x18: /* Highest Pending Interrupt */
return s->current_pending[cpu];
default:
- cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
- (int)offset);
+ hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
return 0;
}
}
case 0x10: /* End Of Interrupt */
return gic_complete_irq(s, cpu, value & 0x3ff);
default:
- cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
- (int)offset);
+ hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
return;
}
gic_update(s);
cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
break;
default:
- cpu_abort(env, "arm_pic_cpu_handler: Bad interrput line %d\n", irq);
+ hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq);
}
}
return 0;
return s->int_level;
default:
- cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
- (int)offset);
+ hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
return 0;
}
}
arm_timer_recalibrate(s, 0);
break;
default:
- cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
- (int)offset);
+ hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
}
arm_timer_update(s);
}
/* ??? Don't know the PrimeCell ID for this device. */
n = offset >> 8;
- if (n > 3)
- cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
+ if (n > 3) {
+ hw_error("sp804_read: Bad timer %d\n", n);
+ }
return arm_timer_read(s->timer[n], offset & 0xff);
}
int n;
n = offset >> 8;
- if (n > 3)
- cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
+ if (n > 3) {
+ hw_error("sp804_write: Bad timer %d\n", n);
+ }
arm_timer_write(s->timer[n], offset & 0xff, value);
}
irq = gic_acknowledge_irq(s->gic, 0);
if (irq == 1023)
- cpu_abort(cpu_single_env, "Interrupt but no vector\n");
+ hw_error("Interrupt but no vector\n");
if (irq >= 32)
irq -= 16;
return irq;
return val;
case 0xd28: /* Configurable Fault Status. */
/* TODO: Implement Fault Status. */
- cpu_abort(cpu_single_env,
- "Not implemented: Configurable Fault Status.");
+ hw_error("Not implemented: Configurable Fault Status.");
return 0;
case 0xd2c: /* Hard Fault Status. */
case 0xd30: /* Debug Fault Status. */
/* TODO: Implement debug registers. */
default:
bad_reg:
- cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
+ hw_error("NVIC: Bad read offset 0x%x\n", offset);
}
}
case 0xd0c: /* Application Interrupt/Reset Control. */
if ((value >> 16) == 0x05fa) {
if (value & 2) {
- cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
+ hw_error("VECTCLRACTIVE not implemented");
}
if (value & 5) {
- cpu_abort(cpu_single_env, "System reset");
+ hw_error("System reset");
}
}
break;
goto bad_reg;
default:
bad_reg:
- cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
+ hw_error("NVIC: Bad write offset 0x%x\n", offset);
}
}
s->gic->nvic = s;
s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
if (env->v7m.nvic)
- cpu_abort(env, "CPU can only have one NVIC\n");
+ hw_error("CPU can only have one NVIC\n");
env->v7m.nvic = s;
register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
return s->gic->in;
s->slave[s->addr]->io(s->slave[s->addr]->opaque,
s->rw, s->reg, &s->val);
else
- cpu_abort(cpu_single_env, "%s: bad slave address %i\n",
- __FUNCTION__, s->addr);
+ hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
}
static void cbus_cycle(struct cbus_priv_s *s)
return 0x0000;
default:
- cpu_abort(cpu_single_env, "%s: bad register %02x\n",
- __FUNCTION__, reg);
+ hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
break;
default:
- cpu_abort(cpu_single_env, "%s: bad register %02x\n",
- __FUNCTION__, reg);
+ hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
return 0x0000;
default:
- cpu_abort(cpu_single_env, "%s: bad register %02x\n",
- __FUNCTION__, reg);
+ hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
break;
default:
- cpu_abort(cpu_single_env, "%s: bad register %02x\n",
- __FUNCTION__, reg);
+ hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
}
}
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
{
- struct fs_dma_ctrl *ctrl = opaque;
- CPUState *env = ctrl->env;
- cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
- addr);
+ hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static void
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- struct fs_dma_ctrl *ctrl = opaque;
- CPUState *env = ctrl->env;
- cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
- addr);
+ hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
}
static void
static void guru_handler(void *opaque, int irq, int level)
{
- struct fs_pic_state *fs = (void *)opaque;
- cpu_abort(fs->env, "%s unsupported exception\n", __func__);
+ hw_error("%s unsupported exception\n", __func__);
}
struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
}
case 6: /* CM_LMBUSCNT */
/* ??? High frequency timer. */
- cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
+ hw_error("integratorcm_read: CM_LMBUSCNT");
case 7: /* CM_AUXOSC */
return s->cm_auxosc;
case 8: /* CM_SDRAM */
return s->cm_init;
case 10: /* CM_REFCT */
/* ??? High frequency timer. */
- cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
+ hw_error("integratorcm_read: CM_REFCT");
case 12: /* CM_FLAGS */
return s->cm_flags;
case 14: /* CM_NVFLAGS */
/* ??? Voltage control unimplemented. */
return 0;
default:
- cpu_abort (cpu_single_env,
- "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
+ hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
+ (int)offset);
return 0;
}
}
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
{
if (value & 8) {
- cpu_abort(cpu_single_env, "Board reset\n");
+ hw_error("Board reset\n");
}
if ((s->cm_init ^ value) & 4) {
integratorcm_do_remap(s, (value & 4) == 0);
/* ??? The CPU irq/fiq is raised when either the core module or base PIC
are active. */
if (s->int_level & (s->irq_enabled | s->fiq_enabled))
- cpu_abort(cpu_single_env, "Core module interrupt\n");
+ hw_error("Core module interrupt\n");
}
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
/* ??? Voltage control unimplemented. */
break;
default:
- cpu_abort (cpu_single_env,
- "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
+ hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
+ (int)offset);
break;
}
}
case 3: /* CP_DECODE */
return 0x11;
default:
- cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
- (int)offset);
+ hw_error("icp_control_read: Bad offset %x\n", (int)offset);
return 0;
}
}
/* Nothing interesting implemented yet. */
break;
default:
- cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
- (int)offset);
+ hw_error("icp_control_write: Bad offset %x\n", (int)offset);
}
}
static CPUReadMemoryFunc *icp_control_readfn[] = {
prescale *= 16;
if (mode == 3 || mode == 0)
- cpu_abort(cpu_single_env,
- "m5206_timer: mode %d not implemented\n", mode);
+ hw_error("m5206_timer: mode %d not implemented\n", mode);
if ((s->tmr & TMR_FRR) == 0)
- cpu_abort(cpu_single_env,
- "m5206_timer: free running mode not implemented\n");
+ hw_error("m5206_timer: free running mode not implemented\n");
/* Assume 66MHz system clock. */
ptimer_set_freq(s->timer, 66000000 / prescale);
case 0x170: return s->uivr[0];
case 0x1b0: return s->uivr[1];
}
- cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
+ hw_error("Bad MBAR read offset 0x%x", (int)offset);
return 0;
}
s->uivr[1] = value;
break;
default:
- cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
+ hw_error("Bad MBAR write offset 0x%x", (int)offset);
break;
}
}
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
if (offset > 0x200) {
- cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
+ hw_error("Bad MBAR read offset 0x%x", (int)offset);
}
if (m5206_mbar_width[offset >> 2] > 1) {
uint16_t val;
int width;
offset &= 0x3ff;
if (offset > 0x200) {
- cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
+ hw_error("Bad MBAR read offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width > 2) {
int width;
offset &= 0x3ff;
if (offset > 0x200) {
- cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
+ hw_error("Bad MBAR read offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width < 4) {
int width;
offset &= 0x3ff;
if (offset > 0x200) {
- cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
+ hw_error("Bad MBAR write offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width > 1) {
int width;
offset &= 0x3ff;
if (offset > 0x200) {
- cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
+ hw_error("Bad MBAR write offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width > 2) {
int width;
offset &= 0x3ff;
if (offset > 0x200) {
- cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
+ hw_error("Bad MBAR write offset 0x%x", (int)offset);
}
width = m5206_mbar_width[offset >> 2];
if (width < 4) {
case 4:
break;
default:
- cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
break;
}
m5208_timer_update(s);
case 4:
return ptimer_get_count(s->timer);
default:
- cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n",
- (int)addr);
+ hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
return 0;
}
}
return 0;
default:
- cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
- (int)addr);
+ hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
return 0;
}
}
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
- (int)addr);
+ hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
static CPUReadMemoryFunc *m5208_sys_readfn[] = {
case 0x184: return s->etdsr;
case 0x188: return s->emrbr;
default:
- cpu_abort(cpu_single_env, "mcf_fec_read: Bad address 0x%x\n",
- (int)addr);
+ hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
return 0;
}
}
s->emrbr = value & 0x7f0;
break;
default:
- cpu_abort(cpu_single_env, "mcf_fec_write Bad address 0x%x\n",
- (int)addr);
+ hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
}
mcf_fec_update(s);
}
case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe5: case 0xe6: case 0xe7:
/* LnIACK */
- cpu_abort(cpu_single_env, "mcf_intc_read: LnIACK not implemented\n");
+ hw_error("mcf_intc_read: LnIACK not implemented\n");
default:
return 0;
}
s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
break;
default:
- cpu_abort(cpu_single_env, "mcf_intc_write: Bad write offset %d\n",
- offset);
+ hw_error("mcf_intc_write: Bad write offset %d\n", offset);
break;
}
mcf_intc_update(s);
return mpcore_timer_read(&s->timer[id], offset & 0xf);
}
bad_reg:
- cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
- (int)offset);
+ hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
return 0;
}
}
return;
bad_reg:
- cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
- (int)offset);
+ hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
}
static CPUReadMemoryFunc *mpcore_priv_readfn[] = {
LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
rgb_to_pixel32bgr : rgb_to_pixel32))
default:
- cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
+ hw_error("unsupported colour depth %i\n",
ds_get_bits_per_pixel(s->ds));
}
int index;
if (nand_flash_ids[chip_id].size == 0) {
- cpu_abort(cpu_single_env, "%s: Unsupported NAND chip ID.\n",
- __FUNCTION__);
+ hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
}
s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s));
nand_init_2048(s);
break;
default:
- cpu_abort(cpu_single_env, "%s: Unsupported NAND block size.\n",
- __FUNCTION__);
+ hw_error("%s: Unsupported NAND block size.\n", __FUNCTION__);
}
pagesize = 1 << s->oob_shift;
uint8_t ret;
if (len > 9)
- cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
- __FUNCTION__, len);
+ hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
if (s->p >= ARRAY_SIZE(s->resp))
ret = 0;
case omap1510:
return 0x03310115;
default:
- cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
+ hw_error("%s: bad mpu model\n", __FUNCTION__);
}
break;
case omap1510:
return 0xfb47002f;
default:
- cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
+ hw_error("%s: bad mpu model\n", __FUNCTION__);
}
break;
}
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
{
if (line >= 16 || line < 0)
- cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
+ hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->handler[line] = handler;
}
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
{
if (row >= 5 || row < 0)
- cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
- __FUNCTION__, col, row);
+ hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
if (down)
s->buttons[row] |= 1 << col;
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
{
if (line >= 16 || line < 0)
- cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
+ hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->handler[line] = handler;
}
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
{
if (start >= s->modules * 32 || start < 0)
- cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
- __FUNCTION__, start);
+ hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
return s->module[start >> 5].in + (start & 31);
}
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
{
if (line >= s->modules * 32 || line < 0)
- cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
+ hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->module[line >> 5].handler[line & 31] = handler;
}
int chipselect)
{
if (chipselect < 0 || chipselect >= s->chnum)
- cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
- __FUNCTION__, chipselect);
+ hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
s->ch[chipselect].txrx = txrx;
s->ch[chipselect].opaque = opaque;
case omap3430:
return 0x1b7ae02f; /* ES 2 */
default:
- cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
+ hw_error("%s: Bad mpu model\n", __FUNCTION__);
}
case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
case omap3430:
return 0x000000f0;
default:
- cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
+ hw_error("%s: Bad mpu model\n", __FUNCTION__);
}
case 0x20c:
case omap3430:
return 0xcafeb7ae; /* ES 2 */
default:
- cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
+ hw_error("%s: Bad mpu model\n", __FUNCTION__);
}
case 0x218: /* DIE_ID_reg */
for (i = mpu->clks; i->name; i ++)
if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
return i;
- cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
+ hw_error("%s: %s not found\n", __FUNCTION__, name);
}
void omap_clk_get(struct clk *clk)
void omap_clk_put(struct clk *clk)
{
if (!(clk->usecount --))
- cpu_abort(cpu_single_env, "%s: %s is not in use\n",
- __FUNCTION__, clk->name);
+ hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
}
static void omap_clk_update(struct clk *clk)
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip)
{
if (cs < 0 || cs > 1)
- cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
+ hw_error("%s: wrong CS %i\n", __FUNCTION__, cs);
s->rfbi.chip[cs] = chip;
}
memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
- cpu_abort(cpu_single_env, "%s: Loading the BootRAM failed.\n",
- __FUNCTION__);
+ hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
}
}
case 0xff02: /* ECC Result of spare area data */
case 0xff03: /* ECC Result of main area data */
case 0xff04: /* ECC Result of spare area data */
- cpu_abort(cpu_single_env, "%s: imeplement ECC\n", __FUNCTION__);
+ hw_error("%s: imeplement ECC\n", __FUNCTION__);
return 0x0000;
}
case 18: /* UARTDMACR */
return s->dmacr;
default:
- cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
+ hw_error("pl011_read: Bad offset %x\n", (int)offset);
return 0;
}
}
case 18: /* UARTDMACR */
s->dmacr = value;
if (value & 3)
- cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
+ hw_error("PL011: DMA not implemented\n");
break;
default:
- cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
+ hw_error("pl011_write: Bad offset %x\n", (int)offset);
}
}
/* Not implemented. */
return 0;
default:
- cpu_abort (cpu_single_env, "pl022_read: Bad offset %x\n",
- (int)offset);
+ hw_error("pl022_read: Bad offset %x\n", (int)offset);
return 0;
}
}
pl022_update(s);
break;
case 0x20: /* DMACR */
- if (value)
- cpu_abort (cpu_single_env, "pl022: DMA not implemented\n");
+ if (value) {
+ hw_error("pl022: DMA not implemented\n");
+ }
break;
default:
- cpu_abort (cpu_single_env, "pl022_write: Bad offset %x\n",
- (int)offset);
+ hw_error("pl022_write: Bad offset %x\n", (int)offset);
}
}
(int)offset);
break;
default:
- cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
break;
}
break;
default:
- cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
break;
}
}
s = qemu_mallocz(sizeof(pl031_state));
iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
- if (iomemtype == -1)
- cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
+ if (iomemtype == -1) {
+ hw_error("pl031_init: Can't register I/O memory\n");
+ }
cpu_register_physical_memory(base, 0x00001000, iomemtype);
case 4: /* KMIIR */
return s->pending | 2;
default:
- cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", (int)offset);
+ hw_error("pl050_read: Bad offset %x\n", (int)offset);
return 0;
}
}
s->clk = value;
return;
default:
- cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", (int)offset);
+ hw_error("pl050_write: Bad offset %x\n", (int)offset);
}
}
static CPUReadMemoryFunc *pl050_readfn[] = {
case 0x524: /* Commit */
return s->cr;
default:
- cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
- (int)offset);
+ hw_error("pl061_read: Bad offset %x\n", (int)offset);
return 0;
}
}
s->cr = value;
break;
default:
- cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
- (int)offset);
+ hw_error("pl061_write: Bad offset %x\n", (int)offset);
}
pl061_update(s);
}
if ((s->conf & PL080_CONF_E) == 0)
return;
-cpu_abort(cpu_single_env, "DMA active\n");
+hw_error("DMA active\n");
/* If we are already in the middle of a DMA operation then indicate that
there may be new DMA requests and return immediately. */
if (s->running) {
continue;
flow = (ch->conf >> 11) & 7;
if (flow >= 4) {
- cpu_abort(cpu_single_env,
+ hw_error(
"pl080_run: Peripheral flow control not implemented\n");
}
src_id = (ch->conf >> 1) & 0x1f;
return s->sync;
default:
bad_offset:
- cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset);
+ hw_error("pl080_read: Bad offset %x\n", (int)offset);
return 0;
}
}
case 10: /* SoftLBReq */
case 11: /* SoftLSReq */
/* ??? Implement these. */
- cpu_abort(cpu_single_env, "pl080_write: Soft DMA not implemented\n");
+ hw_error("pl080_write: Soft DMA not implemented\n");
break;
case 12: /* Configuration */
s->conf = value;
if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
- cpu_abort(cpu_single_env,
- "pl080_write: Big-endian DMA not implemented\n");
+ hw_error("pl080_write: Big-endian DMA not implemented\n");
}
pl080_run(s);
break;
break;
default:
bad_offset:
- cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset);
+ hw_error("pl080_write: Bad offset %x\n", (int)offset);
}
pl080_update(s);
}
case 12: /* LCDLPCURR */
return s->lpbase;
default:
- cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
+ hw_error("pl110_read: Bad offset %x\n", (int)offset);
return 0;
}
}
pl110_update(s);
break;
default:
- cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
+ hw_error("pl110_write: Bad offset %x\n", (int)offset);
}
}
return value;
}
default:
- cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset);
+ hw_error("pl181_read: Bad offset %x\n", (int)offset);
return 0;
}
}
}
break;
default:
- cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset);
+ hw_error("pl181_write: Bad offset %x\n", (int)offset);
}
pl181_update(s);
}
case 13: /* DEFVECTADDR */
return s->vect_addr[16];
default:
- cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset);
+ hw_error("pl190_read: Bad offset %x\n", (int)offset);
return 0;
}
}
s->default_addr = val;
break;
case 0xc0: /* ITCR */
- if (val)
- cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
+ if (val) {
+ hw_error("pl190: Test mode not implemented\n");
+ }
break;
default:
- cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset);
+ hw_error("pl190_write: Bad offset %x\n", (int)offset);
return;
}
pl190_update(s);
/* Load OpenBIOS (ELF) */
bios_size = load_elf(buf, 0, NULL, NULL, NULL);
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
+ hw_error("qemu: could not load PowerPC bios '%s'\n", buf);
exit(1);
}
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
- cpu_abort(env, "qemu: could not load kernel '%s'\n",
- kernel_filename);
+ hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
exit(1);
}
/* load initrd */
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
- cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
- initrd_filename);
+ hw_error("qemu: could not load initial ram disk '%s'\n",
+ initrd_filename);
exit(1);
}
} else {
break;
#endif /* defined(TARGET_PPC64) */
default:
- cpu_abort(env, "Bus model not supported on mac99 machine\n");
+ hw_error("Bus model not supported on mac99 machine\n");
exit(1);
}
}
/* Load OpenBIOS (ELF) */
bios_size = load_elf(buf, 0, NULL, NULL, NULL);
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
+ hw_error("qemu: could not load PowerPC bios '%s'\n", buf);
exit(1);
}
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
- cpu_abort(env, "qemu: could not load kernel '%s'\n",
+ hw_error("qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
- cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
- initrd_filename);
+ hw_error("qemu: could not load initial ram disk '%s'\n",
+ initrd_filename);
exit(1);
}
} else {
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
break;
default:
- cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
- exit(1);
+ hw_error("Bus model not supported on OldWorld Mac machine\n");
}
}
/* init basic PC hardware */
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
- cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
- exit(1);
+ hw_error("Only 6xx bus is supported on heathrow machine\n");
}
pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic);
bios_size = load_image_targphys(buf, bios_addr, bios_size);
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
- exit(1);
+ hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
}
if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
- cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
+ hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
}
if (linux_boot) {
kernel_size = load_image_targphys(kernel_filename, kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
- cpu_abort(env, "qemu: could not load kernel '%s'\n",
- kernel_filename);
+ hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
exit(1);
}
/* load initrd */
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
- cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
+ hw_error("qemu: could not load initial ram disk '%s'\n",
initrd_filename);
- exit(1);
}
} else {
initrd_base = 0;
isa_mem_base = 0xc0000000;
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
- cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
- exit(1);
+ hw_error("Only 6xx bus is supported on PREP machine\n");
}
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
pci_bus = pci_prep_init(i8259);
}
}
- cpu_abort(cpu_single_env,
- "%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
return 7;
}
if (value & DRCMR_MAPVLD)
if ((value & DRCMR_CHLNUM) > s->channels)
- cpu_abort(cpu_single_env, "%s: Bad DMA channel %i\n",
- __FUNCTION__, value & DRCMR_CHLNUM);
+ hw_error("%s: Bad DMA channel %i\n",
+ __FUNCTION__, value & DRCMR_CHLNUM);
s->req[channel] = value;
break;
break;
}
fail:
- cpu_abort(cpu_single_env, "%s: Bad offset " TARGET_FMT_plx "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
}
}
static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset)
{
- cpu_abort(cpu_single_env, "%s: Bad access width\n", __FUNCTION__);
+ hw_error("%s: Bad access width\n", __FUNCTION__);
return 5;
}
static void pxa2xx_dma_writebad(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
- cpu_abort(cpu_single_env, "%s: Bad access width\n", __FUNCTION__);
+ hw_error("%s: Bad access width\n", __FUNCTION__);
}
static CPUReadMemoryFunc *pxa2xx_dma_readfn[] = {
{
int ch;
if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
- cpu_abort(cpu_single_env,
- "%s: Bad DMA request %i\n", __FUNCTION__, req_num);
+ hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
if (!(s->req[req_num] & DRCMR_MAPVLD))
return;
return s->status[bank];
default:
- cpu_abort(cpu_single_env,
- "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
break;
default:
- cpu_abort(cpu_single_env,
- "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
}
return s->kpkdi;
break;
default:
- cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
break;
default:
- cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
}
default:
fail:
- cpu_abort(cpu_single_env,
- "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
default:
fail:
- cpu_abort(cpu_single_env,
- "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
}
case MMC_BLKS_REM:
return s->numblk;
default:
- cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
break;
default:
- cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
}
return s->snapshot;
default:
badreg:
- cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
- REG_FMT "\n", offset);
+ hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
}
return 0;
break;
default:
badreg:
- cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
- REG_FMT "\n", offset);
+ hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
}
}
if (s->feat & TIMER_FEAT_CAPT)
return s->tcpr;
default:
- cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
- (int)offset);
+ hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
return 0;
}
}
case 4: freq >>= 10; break;
case 6:
case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved TPSC value\n"); break;
+ default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
}
switch ((value & TIMER_TCR_CKEG) >> 3) {
case 0: break;
case 1:
case 2:
case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved CKEG value\n"); break;
+ default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
}
switch ((value & TIMER_TCR_ICPE) >> 6) {
case 0: break;
case 2:
case 3: if (s->feat & TIMER_FEAT_CAPT) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved ICPE value\n"); break;
+ default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
}
if ((value & TIMER_TCR_UNF) == 0)
s->int_level = 0;
value &= ~TIMER_TCR_UNF;
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
- cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved ICPF value\n");
+ hw_error("sh_timer_write: Reserved ICPF value\n");
value &= ~TIMER_TCR_ICPF; /* capture not supported */
if (value & TIMER_TCR_RESERVED)
- cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved TCR bits set\n");
+ hw_error("sh_timer_write: Reserved TCR bits set\n");
s->tcr = value;
ptimer_set_limit(s->timer, s->tcor, 0);
ptimer_set_freq(s->timer, freq);
break;
}
default:
- cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
- (int)offset);
+ hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
}
sh_timer_update(s);
}
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
return sh_timer_read(s->timer[2], offset - 0x20);
}
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
return s->tocr;
- cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad offset %x\n", (int)offset);
return 0;
}
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
sh_timer_write(s->timer[2], offset - 0x20, value);
return;
}
sh_timer_start_stop(s->timer[2], value & (1 << 2));
else
if (value & (1 << 2))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
+ hw_error("tmu012_write: Bad channel\n");
s->tstr = value;
return;
}
break;
}
- cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
- s->bank, (int)offset);
+ hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
}
static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
}
break;
}
- cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
- s->bank, (int)offset);
+ hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset);
return 0;
}
} else if (s->mode[n] == 0xa) {
/* PWM mode. Not implemented. */
} else {
- cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
- s->mode[n]);
+ hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
}
s->tick[n] = tick;
qemu_mod_timer(s->timer[n], tick);
} else if (s->mode[n] == 0xa) {
/* PWM mode. Not implemented. */
} else {
- cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
- s->mode[n]);
+ hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
}
gptm_update_irq(s);
}
if (s->control == 1)
return s->rtc;
case 0x4c: /* TBR */
- cpu_abort(cpu_single_env, "TODO: Timer value read\n");
+ hw_error("TODO: Timer value read\n");
default:
- cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset);
+ hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
return 0;
}
}
s->match_prescale[0] = value;
break;
default:
- cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset);
+ hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
}
gptm_update_irq(s);
}
case 0x1e4: /* USER1 */
return s->user1;
default:
- cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
+ hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
return 0;
}
}
s->ldoarst = value;
break;
default:
- cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);
+ hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
}
ssys_update(s);
}
case 0x20: /* MCR */
return s->mcr;
default:
- cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
return 0;
}
}
break;
case 0x20: /* MCR */
if (value & 1)
- cpu_abort(cpu_single_env,
+ hw_error(
"stellaris_i2c_write: Loopback not implemented\n");
if (value & 0x20)
- cpu_abort(cpu_single_env,
+ hw_error(
"stellaris_i2c_write: Slave mode not implemented\n");
s->mcr = value & 0x31;
break;
default:
- cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",
+ hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
(int)offset);
}
stellaris_i2c_update(s);
case 0x30: /* SAC */
return s->sac;
default:
- cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x%x\n",
+ hw_error("strllaris_adc_read: Bad offset 0x%x\n",
(int)offset);
return 0;
}
return;
case 0x04: /* SSCTL */
if (value != 6) {
- cpu_abort(cpu_single_env, "ADC: Unimplemented sequence %x\n",
+ hw_error("ADC: Unimplemented sequence %x\n",
value);
}
s->ssctl[n] = value;
case 0x00: /* ACTSS */
s->actss = value & 0xf;
if (value & 0xe) {
- cpu_abort(cpu_single_env,
- "Not implemented: ADC sequencers 1-3\n");
+ hw_error("Not implemented: ADC sequencers 1-3\n");
}
break;
case 0x08: /* IM */
s->sspri = value;
break;
case 0x28: /* PSSI */
- cpu_abort(cpu_single_env, "Not implemented: ADC sample initiate\n");
+ hw_error("Not implemented: ADC sample initiate\n");
break;
case 0x30: /* SAC */
s->sac = value;
break;
default:
- cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
}
stellaris_adc_update(s);
}
case 0x3c: /* Undocuented: Timestamp? */
return 0;
default:
- cpu_abort (cpu_single_env, "stellaris_enet_read: Bad offset %x\n",
- (int)offset);
+ hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
return 0;
}
}
/* Ignored. */
break;
default:
- cpu_abort (cpu_single_env, "stellaris_enet_write: Bad offset %x\n",
- (int)offset);
+ hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
}
}
ret = tsc2102_audio_register_read(s, s->offset);
break;
default:
- cpu_abort(cpu_single_env, "tsc210x_read: wrong memory page\n");
+ hw_error("tsc210x_read: wrong memory page\n");
}
tsc210x_pin_update(s);
tsc2102_audio_register_write(s, s->offset, value);
break;
default:
- cpu_abort(cpu_single_env,
- "tsc210x_write: wrong memory page\n");
+ hw_error("tsc210x_write: wrong memory page\n");
}
tsc210x_pin_update(s);
uint32_t ret = 0;
if (len != 16)
- cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
- __FUNCTION__, len);
+ hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
/* TODO: sequential reads etc - how do we make sure the host doesn't
* unintentionally read out a conversion result from a register while
s->dev_config = value;
s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
- cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n",
- __FUNCTION__);
+ hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
break;
case TUSB_PHY_OTG_CTRL_ENABLE:
/* TODO: what with low-speed Bulk and Isochronous? */
}
- cpu_abort(cpu_single_env, "bad interval\n");
+ hw_error("bad interval\n");
}
static inline void musb_packet(struct musb_s *s, struct musb_ep_s *ep,