drm/amdgpu/gfx10: re-init clear state buffer after gpu reset

BugLink: https://bugs.launchpad.net/bugs/1860179
commit 210b3b3c7563df391bd81d49c51af303b928de4a upstream.

This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.

clear state buffer (resides in vram) is corrupted after 1st baco reset,
upon gfxoff exit, CPF gets garbage header in CSIB and hangs.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Connor Kuehl <connor.kuehl@canonical.com>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 79dde9af1eb9de64d52436924b6feb181a9d3445..266d2ac85a4cf139cdd3142142317468031312d0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1572,24 +1572,49 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
        WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
 }
 
-static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
+static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
 {
+       int r;
+
+       if (adev->in_gpu_reset) {
+               r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+               if (r)
+                       return r;
+
+               r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
+                                  (void **)&adev->gfx.rlc.cs_ptr);
+               if (!r) {
+                       adev->gfx.rlc.funcs->get_csb_buffer(adev,
+                                       adev->gfx.rlc.cs_ptr);
+                       amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+               }
+
+               amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+               if (r)
+                       return r;
+       }
+
        /* csib */
        WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
                     adev->gfx.rlc.clear_state_gpu_addr >> 32);
        WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
                     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
        WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+
+       return 0;
 }
 
-static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
+static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
 {
-       gfx_v10_0_init_csb(adev);
+       int r;
+       r = gfx_v10_0_init_csb(adev);
+       if (r)
+               return r;
 
        amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
 
        /* TODO: init power gating */
-       return;
+       return 0;
 }
 
 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
@@ -1691,7 +1716,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
                r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
                if (r)
                        return r;
-               gfx_v10_0_init_pg(adev);
+
+               r = gfx_v10_0_init_pg(adev);
+               if (r)
+                       return r;
 
                /* enable RLC SRM */
                gfx_v10_0_rlc_enable_srm(adev);
@@ -1717,7 +1745,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
                                return r;
                }
 
-               gfx_v10_0_init_pg(adev);
+               r = gfx_v10_0_init_pg(adev);
+               if (r)
+                       return r;
+
                adev->gfx.rlc.funcs->start(adev);
 
                if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {