arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55

BugLink: https://bugs.launchpad.net/bugs/1918974
commit c0b15c25d25171db4b70cc0b7dbc1130ee94017d upstream.

The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.

Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
[will: Update Kconfig help text]
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Kelsey Skunberg <kelsey.skunberg@canonical.com>

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1761d2f13172a7f3fb689da8643ac292785c1cd8..b2b1053a68a3ee5c03cf228926090cab66aaf1be 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -489,7 +489,7 @@ config ARM64_ERRATUM_1024718
        help
          This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 
-         Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+         Affected Cortex-A55 cores (all revisions) could cause incorrect
          update of the hardware dirty bit when the DBM/AP bits are updated
          without a break-before-make. The workaround is to disable the usage
          of hardware DBM locally on the affected cores. CPUs not affected by

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f2ec845404149eff92147a8f04bb0644be284dc2..79caab15ccbf794d8da559c94a6ab50307776fce 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1092,7 +1092,7 @@ static bool cpu_has_broken_dbm(void)
        /* List of CPUs which have broken DBM support. */
        static const struct midr_range cpus[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1024718
-               MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
+               MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 #endif
                {},
        };