Push TARGET_WORDS_BIGENDIAN dependency to board level.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
hw-obj-$(CONFIG_M48T59) += m48t59.o
hw-obj-$(CONFIG_ESCC) += escc.o
+hw-obj-$(CONFIG_SERIAL) += serial.o
hw-obj-$(CONFIG_PARALLEL) += parallel.o
hw-obj-$(CONFIG_I8254) += i8254.o
hw-obj-$(CONFIG_PCSPK) += pcspk.o
obj-i386-y = ide/core.o
obj-i386-y += pckbd.o $(sound-obj-y) dma.o
obj-i386-y += vga.o
-obj-i386-y += mc146818rtc.o serial.o i8259.o pc.o
+obj-i386-y += mc146818rtc.o i8259.o pc.o
obj-i386-y += cirrus_vga.o apic.o ioapic.o acpi.o piix_pci.o
obj-i386-y += vmmouse.o vmport.o vmware_vga.o hpet.o
obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
obj-ppc-y = ppc.o ide/core.o ide/macio.o
obj-ppc-y += vga.o $(sound-obj-y) dma.o openpic.o
# PREP target
-obj-ppc-y += pckbd.o serial.o i8259.o mc146818rtc.o
+obj-ppc-y += pckbd.o i8259.o mc146818rtc.o
obj-ppc-y += prep_pci.o ppc_prep.o
# Mac shared devices
obj-ppc-y += macio.o cuda.o adb.o mac_nvram.o mac_dbdma.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
-obj-mips-y += dma.o vga.o serial.o i8259.o rc4030.o
+obj-mips-y += dma.o vga.o i8259.o rc4030.o
obj-mips-y += vga-isa-mm.o
obj-mips-y += g364fb.o jazz_led.o dp8393x.o
obj-mips-y += ide/core.o
obj-sparc-y = sun4u.o pckbd.o apb_pci.o
obj-sparc-y += ide/core.o
obj-sparc-y += vga.o
-obj-sparc-y += mc146818rtc.o serial.o
+obj-sparc-y += mc146818rtc.o
obj-sparc-y += cirrus_vga.o
else
obj-sparc-y = sun4m.o lance.o tcx.o iommu.o slavio_intctl.o
obj-arm-y += pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
obj-arm-y += pflash_cfi01.o gumstix.o
-obj-arm-y += zaurus.o ide/core.o ide/microdrive.o serial.o spitz.o tosa.o tc6393xb.o
+obj-arm-y += zaurus.o ide/core.o ide/microdrive.o spitz.o tosa.o tc6393xb.o
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
obj-arm-y += omap2.o omap_dss.o soc_dma.o
obj-arm-y += omap_sx1.o palm.o tsc210x.o
obj-arm-y += syborg_virtio.o
obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
-obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
+obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o
obj-sh4-y += ide/core.o ide/mmio.o
obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
CONFIG_ISA_MMIO=y
CONFIG_NAND=y
CONFIG_ECC=y
+CONFIG_SERIAL=y
CONFIG_PTIMER=y
CONFIG_SD=y
CONFIG_MAX7310=y
CONFIG_USB_OHCI=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_VGA_PCI=y
+CONFIG_SERIAL=y
CONFIG_I8254=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_VGA_PCI=y
+CONFIG_SERIAL=y
CONFIG_I8254=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_VGA_PCI=y
+CONFIG_SERIAL=y
CONFIG_I8254=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y
# Default configuration for sh4-softmmu
CONFIG_USB_OHCI=y
+CONFIG_SERIAL=y
CONFIG_PTIMER=y
# Default configuration for sh4eb-softmmu
CONFIG_USB_OHCI=y
+CONFIG_SERIAL=y
CONFIG_PTIMER=y
CONFIG_M48T59=y
CONFIG_PTIMER=y
CONFIG_VGA_PCI=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y
CONFIG_USB_OHCI=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
+CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
/* Serial ports */
- if (serial_hds[0])
- serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
- if (serial_hds[1])
- serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
+ if (serial_hds[0]) {
+#ifdef TARGET_WORDS_BIGENDIAN
+ serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
+#else
+ serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
+#endif
+ }
+ if (serial_hds[1]) {
+#ifdef TARGET_WORDS_BIGENDIAN
+ serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
+#else
+ serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
+#endif
+ }
/* Parallel port */
if (parallel_hds[0])
s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init);
- s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
+#ifdef TARGET_WORDS_BIGENDIAN
+ s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1);
+#else
+ s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 0);
+#endif
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);
pic[MP_TIMER4_IRQ], NULL);
if (serial_hds[0]) {
+#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
- serial_hds[0], 1);
+ serial_hds[0], 1, 1);
+#else
+ serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
+ serial_hds[0], 1, 0);
+#endif
}
if (serial_hds[1]) {
+#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
- serial_hds[1], 1);
+ serial_hds[1], 1, 1);
+#else
+ serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
+ serial_hds[1], 1, 0);
+#endif
}
/* Register flash */
s->base = base;
s->fclk = fclk;
s->irq = irq;
+#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
- chr ?: qemu_chr_open("null", "null", NULL), 1);
-
+ chr ?: qemu_chr_open("null", "null", NULL), 1,
+ 1);
+#else
+ s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
+ chr ?: qemu_chr_open("null", "null", NULL), 1,
+ 0);
+#endif
return s;
}
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
{
/* TODO: Should reuse or destroy current s->serial */
+#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(s->base, 2, s->irq,
- omap_clk_getrate(s->fclk) / 16,
- chr ?: qemu_chr_open("null", "null", NULL), 1);
+ omap_clk_getrate(s->fclk) / 16,
+ chr ?: qemu_chr_open("null", "null", NULL), 1,
+ 1);
+#else
+ s->serial = serial_mm_init(s->base, 2, s->irq,
+ omap_clk_getrate(s->fclk) / 16,
+ chr ?: qemu_chr_open("null", "null", NULL), 1,
+ 0);
+#endif
}
/* MPU Clock/Reset/Power Mode Control */
CharDriverState *chr);
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
- CharDriverState *chr, int ioregister);
+ CharDriverState *chr, int ioregister,
+ int be);
SerialState *serial_isa_init(int index, CharDriverState *chr);
void serial_set_frequency(SerialState *s, uint32_t frequency);
/* Serial ports */
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[0], 1);
+ serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[1], 1);
+ serial_hds[1], 1, 1);
}
/* IIC controller */
ppc405_i2c_init(0xef600500, pic[2]);
/* Serial ports */
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[0], 1);
+ serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[1], 1);
+ serial_hds[1], 1, 1);
}
/* OCM */
ppc405_ocm_init(env);
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[0], 1);
+ serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[1], 1);
+ serial_hds[1], 1, 1);
}
return env;
mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
/* Serial */
- if (serial_hds[0])
+ if (serial_hds[0]) {
serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
- 0, mpic[12+26], 399193,
- serial_hds[0], 1);
+ 0, mpic[12+26], 399193,
+ serial_hds[0], 1, 1);
+ }
- if (serial_hds[1])
+ if (serial_hds[1]) {
serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
- 0, mpic[12+26], 399193,
- serial_hds[0], 1);
+ 0, mpic[12+26], 399193,
+ serial_hds[0], 1, 1);
+ }
/* PCI */
pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
+#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa270_serial[i].io_base, 2,
s->pic[pxa270_serial[i].irqn], 14857000/16,
- serial_hds[i], 1);
+ serial_hds[i], 1, 1);
+#else
+ serial_mm_init(pxa270_serial[i].io_base, 2,
+ s->pic[pxa270_serial[i].irqn], 14857000/16,
+ serial_hds[i], 1, 1);
+#endif
else
break;
if (serial_hds[i])
s->pic[PXA2XX_PIC_MMC], s->dma);
for (i = 0; pxa255_serial[i].io_base; i ++)
- if (serial_hds[i])
+ if (serial_hds[i]) {
+#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa255_serial[i].io_base, 2,
s->pic[pxa255_serial[i].irqn], 14745600/16,
- serial_hds[i], 1);
- else
+ serial_hds[i], 1, 1);
+#else
+ serial_mm_init(pxa255_serial[i].io_base, 2,
+ s->pic[pxa255_serial[i].irqn], 14745600/16,
+ serial_hds[i], 1, 0);
+#endif
+ } else {
break;
+ }
if (serial_hds[i])
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
-#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
-#endif
return val;
}
-static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
+ uint32_t val;
+
+ val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
+ return val;
+}
+
+static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ SerialState *s = opaque;
+
value = bswap16(value);
-#endif
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
+static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ SerialState *s = opaque;
+
+ serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
+}
+
+static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
val = serial_ioport_read(s, addr >> s->it_shift);
-#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
-#endif
return val;
}
-static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr)
+{
+ SerialState *s = opaque;
+ uint32_t val;
+
+ val = serial_ioport_read(s, addr >> s->it_shift);
+ return val;
+}
+
+static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
{
SerialState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
+
value = bswap32(value);
-#endif
serial_ioport_write(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc * const serial_mm_read[] = {
+static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ SerialState *s = opaque;
+
+ serial_ioport_write(s, addr >> s->it_shift, value);
+}
+
+static CPUReadMemoryFunc * const serial_mm_read_be[] = {
&serial_mm_readb,
- &serial_mm_readw,
- &serial_mm_readl,
+ &serial_mm_readw_be,
+ &serial_mm_readl_be,
};
-static CPUWriteMemoryFunc * const serial_mm_write[] = {
+static CPUWriteMemoryFunc * const serial_mm_write_be[] = {
&serial_mm_writeb,
- &serial_mm_writew,
- &serial_mm_writel,
+ &serial_mm_writew_be,
+ &serial_mm_writel_be,
+};
+
+static CPUReadMemoryFunc * const serial_mm_read_le[] = {
+ &serial_mm_readb,
+ &serial_mm_readw_le,
+ &serial_mm_readl_le,
+};
+
+static CPUWriteMemoryFunc * const serial_mm_write_le[] = {
+ &serial_mm_writeb,
+ &serial_mm_writew_le,
+ &serial_mm_writel_le,
};
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
- CharDriverState *chr, int ioregister)
+ CharDriverState *chr, int ioregister,
+ int be)
{
SerialState *s;
int s_io_memory;
vmstate_register(base, &vmstate_serial, s);
if (ioregister) {
- s_io_memory = cpu_register_io_memory(serial_mm_read,
- serial_mm_write, s);
+ if (be) {
+ s_io_memory = cpu_register_io_memory(serial_mm_read_be,
+ serial_mm_write_be, s);
+ } else {
+ s_io_memory = cpu_register_io_memory(serial_mm_read_le,
+ serial_mm_write_le, s);
+ }
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
}
serial_update_msl(s);
2, -1, irq);
/* bridge to serial emulation module */
- if (chr)
- serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
- NULL, /* TODO : chain irq to IRL */
- 115200, chr, 1);
+ if (chr) {
+#ifdef TARGET_WORDS_BIGENDIAN
+ serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
+ NULL, /* TODO : chain irq to IRL */
+ 115200, chr, 1, 1);
+#else
+ serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
+ NULL, /* TODO : chain irq to IRL */
+ 115200, chr, 1, 0);
+#endif
+ }
/* create qemu graphic console */
s->ds = graphic_console_init(sm501_update_display, NULL,
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
- serial_hds[i], 1);
+ serial_hds[i], 1, 1);
i++;
}
for(; i < MAX_SERIAL_PORTS; i++) {
projects / qemu.git / commitdiff