#define float32_snan_to_qnan(x) ((x) | 0x00400000)
#define float16_snan_to_qnan(x) ((x) | 0x0200)
+static inline float32 bfp32_neg(float32 a)
+{
+ if (unlikely(float32_is_any_nan(a))) {
+ return a;
+ } else {
+ return float32_chs(a);
+ }
+}
+
static inline bool fp_exceptions_enabled(CPUPPCState *env)
{
#ifdef CONFIG_USER_ONLY
do_fpscr_check_status(env, retaddr);
}
+typedef float64 extract_f16(float16, float_status *);
+
+static float64 extract_hf16(float16 in, float_status *fp_status)
+{
+ return float16_to_float64(in, true, fp_status);
+}
+
+static void vsxger16(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
+ ppc_acc_t *at, uint32_t mask, bool acc,
+ bool neg_mul, bool neg_acc, extract_f16 extract)
+{
+ float32 r, aux_acc;
+ float64 psum, va, vb, vc, vd;
+ int i, j, xmsk_bit, ymsk_bit;
+ uint8_t pmsk = FIELD_EX32(mask, GER_MSK, PMSK),
+ xmsk = FIELD_EX32(mask, GER_MSK, XMSK),
+ ymsk = FIELD_EX32(mask, GER_MSK, YMSK);
+ float_status *excp_ptr = &env->fp_status;
+ for (i = 0, xmsk_bit = 1 << 3; i < 4; i++, xmsk_bit >>= 1) {
+ for (j = 0, ymsk_bit = 1 << 3; j < 4; j++, ymsk_bit >>= 1) {
+ if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) {
+ va = !(pmsk & 2) ? float64_zero :
+ extract(a->VsrHF(2 * i), excp_ptr);
+ vb = !(pmsk & 2) ? float64_zero :
+ extract(b->VsrHF(2 * j), excp_ptr);
+ vc = !(pmsk & 1) ? float64_zero :
+ extract(a->VsrHF(2 * i + 1), excp_ptr);
+ vd = !(pmsk & 1) ? float64_zero :
+ extract(b->VsrHF(2 * j + 1), excp_ptr);
+ psum = float64_mul(va, vb, excp_ptr);
+ psum = float64r32_muladd(vc, vd, psum, 0, excp_ptr);
+ r = float64_to_float32(psum, excp_ptr);
+ if (acc) {
+ aux_acc = at[i].VsrSF(j);
+ if (neg_mul) {
+ r = bfp32_neg(r);
+ }
+ if (neg_acc) {
+ aux_acc = bfp32_neg(aux_acc);
+ }
+ r = float32_add(r, aux_acc, excp_ptr);
+ }
+ at[i].VsrSF(j) = r;
+ } else {
+ at[i].VsrSF(j) = float32_zero;
+ }
+ }
+ }
+ vsxger_excp(env, GETPC());
+}
+
typedef void vsxger_zero(ppc_vsr_t *at, int, int);
typedef void vsxger_muladd_f(ppc_vsr_t *, ppc_vsr_t *, ppc_vsr_t *, int, int,
vsxger_excp(env, GETPC());
}
+QEMU_FLATTEN
+void helper_XVF16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
+ ppc_acc_t *at, uint32_t mask)
+{
+ vsxger16(env, a, b, at, mask, false, false, false, extract_hf16);
+}
+
+QEMU_FLATTEN
+void helper_XVF16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
+ ppc_acc_t *at, uint32_t mask)
+{
+ vsxger16(env, a, b, at, mask, true, false, false, extract_hf16);
+}
+
+QEMU_FLATTEN
+void helper_XVF16GER2PN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
+ ppc_acc_t *at, uint32_t mask)
+{
+ vsxger16(env, a, b, at, mask, true, false, true, extract_hf16);
+}
+
+QEMU_FLATTEN
+void helper_XVF16GER2NP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
+ ppc_acc_t *at, uint32_t mask)
+{
+ vsxger16(env, a, b, at, mask, true, true, false, extract_hf16);
+}
+
+QEMU_FLATTEN
+void helper_XVF16GER2NN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
+ ppc_acc_t *at, uint32_t mask)
+{
+ vsxger16(env, a, b, at, mask, true, true, true, extract_hf16);
+}
+
QEMU_FLATTEN
void helper_XVF32GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, acc, i32)
+DEF_HELPER_5(XVF16GER2, void, env, vsr, vsr, acc, i32)
+DEF_HELPER_5(XVF16GER2PP, void, env, vsr, vsr, acc, i32)
+DEF_HELPER_5(XVF16GER2PN, void, env, vsr, vsr, acc, i32)
+DEF_HELPER_5(XVF16GER2NP, void, env, vsr, vsr, acc, i32)
+DEF_HELPER_5(XVF16GER2NN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GER, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GERPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GERPN, void, env, vsr, vsr, acc, i32)