ARM: dts: tegra20/tegra30: add pmu interrupt-affinity

This is similar to tegra124 and avoids the following being reported
upon boot:

hw perfevents: no interrupt-affinity property for /pmu, guessing.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 80854f7de765c571a628a8f5c1846a47a377079f..20869757d32f46f9fa264e83f86724d22284dc91 100644 (file)
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -865,5 +865,7 @@
                compatible = "arm,cortex-a9-pmu";
                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&{/cpus/cpu@0}>,
+                                    <&{/cpus/cpu@1}>;
        };
 };

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5a04ddefb71f62013d2ce5991fb56beaf47b184e..d2b553f76719070e58284a49c3b62fd2c0c491be 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1013,5 +1013,9 @@
                             <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&{/cpus/cpu@0}>,
+                                    <&{/cpus/cpu@1}>,
+                                    <&{/cpus/cpu@2}>,
+                                    <&{/cpus/cpu@3}>;
        };
 };