ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk

The dbg_base_clk can also have osc1 has a parent.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6fff9c08a3d9b0dc0b8b06b62c06da286e..01bdaaa508541a8b967da5bec0712fd3e67d9450 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -164,7 +164,7 @@
                                                dbg_base_clk: dbg_base_clk {
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
-                                                       clocks = <&main_pll>;
+                                                       clocks = <&main_pll>, <&osc1>;
                                                        div-reg = <0xe8 0 9>;
                                                        reg = <0x50>;
                                                };