#define IS_IMM (insn & (1<<13))
-static void disas_sparc_insn(DisasContext * dc);
-
/* floating point registers moves */
static void gen_op_load_fpr_FT0(unsigned int src)
{
#define ABI32_MASK(addr)
#endif
-static inline void gen_movl_simm_T1(int32_t val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
static inline void gen_movl_reg_TN(int reg, TCGv tn)
{
if (reg == 0)
}
}
-static inline void gen_movl_reg_T0(int reg)
-{
- gen_movl_reg_TN(reg, cpu_T[0]);
-}
-
-static inline void gen_movl_reg_T1(int reg)
-{
- gen_movl_reg_TN(reg, cpu_T[1]);
-}
-
-#ifdef __i386__
-static inline void gen_movl_reg_T2(int reg)
-{
- gen_movl_reg_TN(reg, cpu_T[2]);
-}
-
-#endif /* __i386__ */
static inline void gen_movl_TN_reg(int reg, TCGv tn)
{
if (reg == 0)
}
}
-static inline void gen_movl_T0_reg(int reg)
-{
- gen_movl_TN_reg(reg, cpu_T[0]);
-}
-
-static inline void gen_movl_T1_reg(int reg)
-{
- gen_movl_TN_reg(reg, cpu_T[1]);
-}
-
-static inline void gen_op_movl_T0_env(size_t offset)
-{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offset);
- tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
-}
-
-static inline void gen_op_movl_env_T0(size_t offset)
-{
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offset);
-}
-
-static inline void gen_op_movtl_T0_env(size_t offset)
-{
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
-}
-
-static inline void gen_op_movtl_env_T0(size_t offset)
-{
- tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
-}
-
-static inline void gen_op_add_T1_T0(void)
-{
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_or_T1_T0(void)
-{
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_xor_T1_T0(void)
-{
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_jmp_im(target_ulong pc)
-{
- tcg_gen_movi_tl(cpu_pc, pc);
-}
-
-static inline void gen_movl_npc_im(target_ulong npc)
-{
- tcg_gen_movi_tl(cpu_npc, npc);
-}
-
static inline void gen_goto_tb(DisasContext *s, int tb_num,
target_ulong pc, target_ulong npc)
{
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
- gen_jmp_im(pc);
- gen_movl_npc_im(npc);
+ tcg_gen_movi_tl(cpu_pc, pc);
+ tcg_gen_movi_tl(cpu_npc, npc);
tcg_gen_exit_tb((long)tb + tb_num);
} else {
/* jump to another page: currently not optimized */
- gen_jmp_im(pc);
- gen_movl_npc_im(npc);
+ tcg_gen_movi_tl(cpu_pc, pc);
+ tcg_gen_movi_tl(cpu_npc, npc);
tcg_gen_exit_tb(0);
}
}
tcg_gen_andi_tl(reg, reg, 0x1);
}
-static inline void gen_op_exception(int exception)
-{
- tcg_gen_movi_i32(cpu_tmp32, exception);
- tcg_gen_helper_0_1(raise_exception, cpu_tmp32);
-}
-
static inline void gen_cc_clear(void)
{
tcg_gen_movi_i32(cpu_psr, 0);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
- gen_op_exception(TT_TOVF);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l1);
#ifdef TARGET_SPARC64
{
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
- gen_op_exception(TT_TOVF);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l2);
}
#endif
tcg_gen_or_tl(cpu_tmp0, src1, src2);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
- gen_op_exception(TT_TOVF);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l1);
}
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
- gen_op_exception(TT_TOVF);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l1);
#ifdef TARGET_SPARC64
{
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
- gen_op_exception(TT_TOVF);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l2);
}
#endif
tcg_gen_discard_i64(r_temp2);
}
-static inline void gen_op_udiv_T1_T0(void)
-{
- tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_sdiv_T1_T0(void)
-{
- tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
#ifdef TARGET_SPARC64
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
{
l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
- gen_op_exception(TT_DIV_ZERO);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
gen_set_label(l1);
}
gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
}
-static inline void gen_branch(DisasContext *dc, target_ulong pc,
- target_ulong npc)
-{
- gen_goto_tb(dc, 0, pc, npc);
-}
-
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
TCGv r_cond)
{
tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
- gen_movl_npc_im(npc1);
+ tcg_gen_movi_tl(cpu_npc, npc1);
tcg_gen_br(l2);
gen_set_label(l1);
- gen_movl_npc_im(npc2);
+ tcg_gen_movi_tl(cpu_npc, npc2);
gen_set_label(l2);
}
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
dc->npc = DYNAMIC_PC;
} else if (dc->npc != DYNAMIC_PC) {
- gen_movl_npc_im(dc->npc);
+ tcg_gen_movi_tl(cpu_npc, dc->npc);
}
}
static inline void save_state(DisasContext * dc)
{
- gen_jmp_im(dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
save_npc(dc);
}
{
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
- gen_op_exception(TT_FP_EXCP);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
}
static int gen_trap_ifnofpu(DisasContext * dc)
#if !defined(CONFIG_USER_ONLY)
if (!dc->fpu_enabled) {
save_state(dc);
- gen_op_exception(TT_NFPU_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
dc->is_br = 1;
return 1;
}
target = sign_extend(target, 16);
target <<= 2;
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
do_branch_reg(dc, target, insn);
goto jmp_insn;
}
#endif
uint32_t value = GET_FIELD(insn, 10, 31);
tcg_gen_movi_tl(cpu_T[0], value << 10);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
#if defined(OPTIM)
}
#endif
int cond;
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) {
rs2 = GET_FIELD(insn, 25, 31);
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
#if defined(OPTIM)
if (rs2 != 0) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
SPARCv8 manual, rdy on the
microSPARC II */
#endif
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, y));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x3: /* V9 rdasi */
- gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x4: /* V9 rdtick */
{
offsetof(CPUState, tick));
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
r_tickptr);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
tcg_gen_discard_ptr(r_tickptr);
}
break;
case 0x5: /* V9 rdpc */
tcg_gen_movi_tl(cpu_T[0], dc->pc);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x6: /* V9 rdfprs */
- gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0xf: /* V9 membar */
break; /* no effect */
case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x17: /* Tick compare */
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tick_cmpr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x18: /* System tick */
{
offsetof(CPUState, stick));
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
r_tickptr);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
tcg_gen_discard_ptr(r_tickptr);
}
break;
case 0x19: /* System tick compare */
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, stick_cmpr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x10: /* Performance Control */
case 0x11: /* Performance Instrumentation Counter */
// gen_op_rdhtstate();
break;
case 3: // hintp
- gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 5: // htba
- gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 6: // hver
- gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 31: // hstick_cmpr
- gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
break;
default:
goto illegal_insn;
}
#endif
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
if (!supervisor(dc))
offsetof(CPUState, tick));
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
r_tickptr);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
tcg_gen_discard_ptr(r_tickptr);
}
break;
case 5: // tba
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
break;
case 6: // pstate
- gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 7: // tl
- gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 8: // pil
- gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 9: // cwp
tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
break;
case 10: // cansave
- gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 11: // canrestore
- gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 12: // cleanwin
- gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 13: // otherwin
- gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 14: // wstate
- gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 16: // UA2005 gl
- gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 26: // UA2005 strand status
if (!hypervisor(dc))
goto priv_insn;
- gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 31: // ver
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, version));
break;
case 15: // fq
default:
goto illegal_insn;
}
#else
- gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
#endif
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
#ifdef TARGET_SPARC64
#else
if (!supervisor(dc))
goto priv_insn;
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
#endif
break;
#endif
l1 = gen_new_label();
cond = GET_FIELD_SP(insn, 14, 17);
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
tcg_const_tl(0), l1);
gen_op_load_fpr_FT0(rs2);
l1 = gen_new_label();
cond = GET_FIELD_SP(insn, 14, 17);
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
tcg_const_tl(0), l1);
gen_op_load_fpr_DT0(DFPREG(rs2));
l1 = gen_new_label();
cond = GET_FIELD_SP(insn, 14, 17);
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
tcg_const_tl(0), l1);
gen_op_load_fpr_QT0(QFPREG(rs2));
tcg_gen_movi_tl(cpu_T[0], (int)rs2);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T0(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[0]);
}
} else {
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
// or x, %g0, y -> mov T1, x; mov y, T1
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) {
- gen_movl_reg_T1(rs2);
- gen_op_or_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
#endif
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
} else if (xop == 0x26) { /* srl, V9 srlx */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
} else if (xop == 0x27) { /* sra, V9 srax */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
#endif
} else if (xop < 0x36) {
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
if (xop < 0x20) {
switch (xop & ~0x10) {
if (xop & 0x10)
gen_op_add_T1_T0_cc();
else
- gen_op_add_T1_T0();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
case 0x1:
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
#endif
case 0xe:
- gen_op_udiv_T1_T0();
+ tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10)
gen_op_div_cc();
break;
case 0xf:
- gen_op_sdiv_T1_T0();
+ tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10)
gen_op_div_cc();
break;
default:
goto illegal_insn;
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
} else {
switch (xop) {
case 0x20: /* taddcc */
gen_op_tadd_T1_T0_cc();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x21: /* tsubcc */
gen_op_tsub_T1_T0_cc();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x22: /* taddcctv */
save_state(dc);
gen_op_tadd_T1_T0_ccTV();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x23: /* tsubcctv */
save_state(dc);
gen_op_tsub_T1_T0_ccTV();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x24: /* mulscc */
gen_op_mulscc_T1_T0();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#ifndef TARGET_SPARC64
case 0x25: /* sll */
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x26: /* srl */
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x27: /* sra */
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#endif
case 0x30:
{
switch(rd) {
case 0: /* wry */
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, y));
break;
#ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the
break;
#else
case 0x2: /* V9 wrccr */
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
break;
case 0x3: /* V9 wrasi */
- gen_op_xor_T1_T0();
- gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
break;
case 0x6: /* V9 wrfprs */
- gen_op_xor_T1_T0();
- gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
{
TCGv r_tickptr;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState,
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
tick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
{
TCGv r_tickptr;
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
+ cpu_T[1]);
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, stick));
{
TCGv r_tickptr;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState,
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
stick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
goto illegal_insn;
}
#else
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
save_state(dc);
gen_op_next_insn();
{
if (!supervisor(dc))
goto priv_insn;
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#ifdef TARGET_SPARC64
switch (rd) {
case 0: // tpc
}
break;
case 5: // tba
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
break;
case 6: // pstate
save_state(dc);
dc->is_br = 1;
break;
case 7: // tl
- gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
break;
case 8: // pil
- gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
break;
case 9: // cwp
tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
break;
case 10: // cansave
- gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
break;
case 11: // canrestore
- gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
break;
case 12: // cleanwin
- gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
break;
case 13: // otherwin
- gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
break;
case 14: // wstate
- gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
break;
case 16: // UA2005 gl
- gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
break;
case 26: // UA2005 strand status
if (!hypervisor(dc))
goto priv_insn;
- gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
break;
default:
goto illegal_insn;
}
#else
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
- gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
#endif
}
break;
#ifndef TARGET_SPARC64
if (!supervisor(dc))
goto priv_insn;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
#else
if (!hypervisor(dc))
goto priv_insn;
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
switch (rd) {
case 0: // hpstate
// XXX gen_op_wrhpstate();
// XXX gen_op_wrhtstate();
break;
case 3: // hintp
- gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
break;
case 5: // htba
- gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
break;
case 31: // hstick_cmpr
{
TCGv r_tickptr;
- gen_op_movtl_env_T0(offsetof(CPUSPARCState,
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
hstick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 10);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
gen_set_label(l1);
tcg_gen_discard_tl(r_cond);
break;
}
case 0x2d: /* V9 sdivx */
gen_op_sdivx_T1_T0();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x2e: /* V9 popc */
{
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 12);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
// XXX optimize: popc(constant)
}
else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
tcg_gen_helper_1_1(helper_popc, cpu_T[0],
cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
}
case 0x2f: /* V9 movr */
{
int l1;
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
l1 = gen_new_label();
tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 9);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
gen_set_label(l1);
break;
}
// XXX
goto illegal_insn;
case 0x010: /* VIS I array8 */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x012: /* VIS I array16 */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
cpu_T[1]);
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x014: /* VIS I array32 */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
cpu_T[1]);
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x018: /* VIS I alignaddr */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x019: /* VIS II bmask */
case 0x01a: /* VIS I alignaddrl */
} else if (xop == 0x39) { /* V9 return */
rs1 = GET_FIELD(insn, 13, 17);
save_state(dc);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
#if defined(OPTIM)
if (rs2) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
#endif
} else {
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
#if defined(OPTIM)
if (rs2) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
{
if (rd != 0) {
tcg_gen_movi_tl(cpu_T[1], dc->pc);
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
}
gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
case 0x3c: /* save */
save_state(dc);
tcg_gen_helper_0_0(helper_save);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x3d: /* restore */
save_state(dc);
tcg_gen_helper_0_0(helper_restore);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
case 0x3e: /* V9 done/retry */
unsigned int xop = GET_FIELD(insn, 7, 12);
rs1 = GET_FIELD(insn, 13, 17);
save_state(dc);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (xop == 0x3c || xop == 0x3e)
{
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
else if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
#if defined(OPTIM)
if (rs2 != 0) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL);
- gen_movl_T0_reg(rd + 1);
+ gen_movl_TN_reg(rd + 1, cpu_T[0]);
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL);
break;
case 0x0f: /* swap register with memory. Also atomically */
gen_op_check_align_T0_3();
- gen_movl_reg_T1(rd);
+ gen_movl_reg_TN(rd, cpu_T[1]);
ABI32_MASK(cpu_T[0]);
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
goto illegal_insn;
gen_op_check_align_T0_7();
gen_ldda_asi(insn);
- gen_movl_T0_reg(rd + 1);
+ gen_movl_TN_reg(rd + 1, cpu_T[0]);
break;
case 0x19: /* load signed byte alternate */
#ifndef TARGET_SPARC64
goto priv_insn;
#endif
gen_op_check_align_T0_3();
- gen_movl_reg_T1(rd);
+ gen_movl_reg_TN(rd, cpu_T[1]);
gen_swap_asi(insn);
break;
default:
goto illegal_insn;
}
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
#ifdef TARGET_SPARC64
skip_move: ;
#endif
}
} else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
xop == 0xe || xop == 0x1e) {
- gen_movl_reg_T1(rd);
+ gen_movl_reg_TN(rd, cpu_T[1]);
switch (xop) {
case 0x4: /* store word */
gen_op_check_align_T0_3();
#else /* __i386__ */
gen_op_check_align_T0_7();
flush_T2(dc);
- gen_movl_reg_T2(rd + 1);
+ gen_movl_reg_TN(rd + 1, cpu_T[2]);
gen_op_ldst(std);
#endif /* __i386__ */
break;
case 0x3c: /* V9 casa */
gen_op_check_align_T0_3();
gen_cas_asi(insn, rd);
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
break;
case 0x3e: /* V9 casxa */
gen_op_check_align_T0_7();
gen_casx_asi(insn, rd);
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
break;
#else
case 0x34: /* stc */
return;
illegal_insn:
save_state(dc);
- gen_op_exception(TT_ILL_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
dc->is_br = 1;
return;
#if !defined(CONFIG_USER_ONLY)
priv_insn:
save_state(dc);
- gen_op_exception(TT_PRIV_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
dc->is_br = 1;
return;
nfpu_insn:
#ifndef TARGET_SPARC64
ncp_insn:
save_state(dc);
- gen_op_exception(TT_NCP_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
dc->is_br = 1;
return;
#endif
/* if single step mode, we generate only one instruction and
generate an exception */
if (env->singlestep_enabled) {
- gen_jmp_im(dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
tcg_gen_exit_tb(0);
break;
}
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
- gen_branch(dc, dc->pc, dc->npc);
+ gen_goto_tb(dc, 0, dc->pc, dc->npc);
} else {
if (dc->pc != DYNAMIC_PC)
- gen_jmp_im(dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
save_npc(dc);
tcg_gen_exit_tb(0);
}
projects / mirror_qemu.git / commitdiff