MIPS: Add R16000 detection

This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those.  Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9092/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 8245875f8b33be3156cfe42b63b0f1d788afebf8..33f3cab9e6891ce7d465ce46422627a8841ea8ed 100644 (file)
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -157,6 +157,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
 #endif
 #ifdef CONFIG_SYS_HAS_CPU_RM7000
        case CPU_RM7000:

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 15903cad1c6f54e0eb43c055b731fadfa8dc807e..fd2e893e9d9f7d0a28fd48b04d3ea10be8b090a5 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -67,7 +67,7 @@
 #define PRID_IMP_R4300         0x0b00
 #define PRID_IMP_VR41XX                0x0c00
 #define PRID_IMP_R12000                0x0e00
-#define PRID_IMP_R14000                0x0f00
+#define PRID_IMP_R14000                0x0f00          /* R14K && R16K */
 #define PRID_IMP_R8000         0x1000
 #define PRID_IMP_PR4450                0x1200
 #define PRID_IMP_R4600         0x2000
@@ -284,8 +284,8 @@ enum cpu_type_enum {
        CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
        CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
        CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
-       CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
-       CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+       CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
+       CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
        CPU_SR71000, CPU_TX49XX,
 
        /*

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1bae00678b9bcc39a27536b4711d88e5d63db3f2..cb436f585bfa03cb671018b17651505797d79998 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -852,8 +852,13 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                c->tlbsize = 64;
                break;
        case PRID_IMP_R14000:
-               c->cputype = CPU_R14000;
-               __cpu_name[cpu] = "R14000";
+               if (((c->processor_id >> 4) & 0x0f) > 2) {
+                       c->cputype = CPU_R16000;
+                       __cpu_name[cpu] = "R16000";
+               } else {
+                       c->cputype = CPU_R14000;
+                       __cpu_name[cpu] = "R14000";
+               }
                set_isa(c, MIPS_CPU_ISA_IV);
                c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                             MIPS_CPU_FPU | MIPS_CPU_32FPR |

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 9d90efea8bb0d6ad8a8a46a6564c778dd9817681..192e7f59245e5b403ed31d75d83b08ccf75c17c3 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -777,6 +777,7 @@ static int n_counters(void)
 
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
                counters = 4;
                break;
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3f8059602765ea9703841715e15c60a72ab1d123..58e2eeddc39181e1f9e6f3ceb47a748119676ebc 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -430,6 +430,7 @@ static inline void local_r4k___flush_cache_all(void * args)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
                /*
                 * These caches are inclusive caches, that is, if something
                 * is not cached in the S-cache, we know it also won't be
@@ -506,7 +507,7 @@ static inline void local_r4k_flush_cache_mm(void * args)
 
        /*
         * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
-        * only flush the primary caches but R10000 and R12000 behave sane ...
+        * only flush the primary caches but R1x000 behave sane ...
         * R4000SC and R4400SC indexed S-cache ops also invalidate primary
         * caches, so we can bail out early.
         */
@@ -1012,6 +1013,7 @@ static void probe_pcache(void)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
                icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
                c->icache.linesz = 64;
                c->icache.ways = 2;
@@ -1223,8 +1225,8 @@ static void probe_pcache(void)
                dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
 
        /*
-        * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
-        * 2-way virtually indexed so normally would suffer from aliases.  So
+        * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
+        * virtually indexed so normally would suffer from aliases.  So
         * normally they'd suffer from aliases but magic in the hardware deals
         * with that for us so we don't need to take care ourselves.
         */
@@ -1240,6 +1242,7 @@ static void probe_pcache(void)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
                break;
 
        case CPU_74K:
@@ -1438,6 +1441,7 @@ static void setup_scache(void)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
                scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
                c->scache.linesz = 64 << ((config >> 13) & 1);
                c->scache.ways = 2;

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 3f85f921801b84f7f91cd67e42bbe528552d6860..885d73ffd6fb470ff237916784ef283c19b5c7eb 100644 (file)
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -157,6 +157,7 @@ static void set_prefetch_parameters(void)
                case CPU_R10000:
                case CPU_R12000:
                case CPU_R14000:
+               case CPU_R16000:
                        /*
                         * Those values have been experimentally tuned for an
                         * Origin 200.

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index b2afa49beab082116e282f8b043cb2a65e4c06ce..37ad381c3e5f0002452f59bc67ef054806a1f390 100644 (file)
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -477,7 +477,8 @@ static void r4k_tlb_configure(void)
        write_c0_wired(0);
        if (current_cpu_type() == CPU_R10000 ||
            current_cpu_type() == CPU_R12000 ||
-           current_cpu_type() == CPU_R14000)
+           current_cpu_type() == CPU_R14000 ||
+           current_cpu_type() == CPU_R16000)
                write_c0_framemask(0);
 
        if (cpu_has_rixi) {

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d75ff73a20120bf28d919b7b6b5bf30a22b5088f..7c7469f56ec30211d243b8b431107f36b2dc11ca 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -569,6 +569,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
        case CPU_4KC:
        case CPU_4KEC:
        case CPU_M14KC:

diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index a26cbe372e061602392650b67f62777992b85bed..81f58958cf081bf8f307f47c1dd4a3a93e82c5cd 100644 (file)
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -98,6 +98,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
        case CPU_XLR:
                lmodel = &op_model_mipsxx_ops;
                break;

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index d6b9e69e7c6998ee807c455848801c0c1716f75f..6a6e2cc55b8926975fb17f9f54649a0a634018c5 100644 (file)
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -296,6 +296,7 @@ static inline int n_counters(void)
 
        case CPU_R12000:
        case CPU_R14000:
+       case CPU_R16000:
                counters = 4;
                break;
 
@@ -411,6 +412,10 @@ static int __init mipsxx_init(void)
                op_model_mipsxx_ops.cpu_type = "mips/r12000";
                break;
 
+       case CPU_R16000:
+               op_model_mipsxx_ops.cpu_type = "mips/r16000";
+               break;
+
        case CPU_SB1:
        case CPU_SB1A:
                op_model_mipsxx_ops.cpu_type = "mips/sb1";