#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
PORT_RC | PORT_PLC | PORT_PE)
-/* USB 3 BOS descriptor and a capability descriptors, combined.
- * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
- */
-static u8 usb_bos_descriptor [] = {
- USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
- USB_DT_BOS, /* __u8 bDescriptorType */
- 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
- 0x1, /* __u8 bNumDeviceCaps */
- /* First device capability, SuperSpeed */
- USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
- USB_DT_DEVICE_CAPABILITY, /* Device Capability */
- USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
- 0x00, /* bmAttributes, LTM off by default */
- USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
- 0x03, /* bFunctionalitySupport,
- USB 3.0 speed only */
- 0x00, /* bU1DevExitLat, set later. */
- 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
- /* Second device capability, SuperSpeedPlus */
- 0x1c, /* bLength 28, will be adjusted later */
- USB_DT_DEVICE_CAPABILITY, /* Device Capability */
- USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
- 0x00, /* bReserved 0 */
- 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
- 0x01, 0x00, /* wFunctionalitySupport */
- 0x00, 0x00, /* wReserved 0 */
- /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
- 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
- 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
- 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
- 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
-};
-
/* Default sublink speed attribute of each lane */
static u32 ssp_cap_default_ssa[] = {
0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
return le16_to_cpu(bos->wTotalLength);
}
-static __maybe_unused int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
- u16 wLength)
-{
- struct xhci_port_cap *port_cap = NULL;
- int i, ssa_count;
- u32 temp;
- u16 desc_size, ssp_cap_size, ssa_size = 0;
- bool usb3_1 = false;
-
- desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
- ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
-
- /* does xhci support USB 3.1 Enhanced SuperSpeed */
- for (i = 0; i < xhci->num_port_caps; i++) {
- if (xhci->port_caps[i].maj_rev == 0x03 &&
- xhci->port_caps[i].min_rev >= 0x01) {
- usb3_1 = true;
- port_cap = &xhci->port_caps[i];
- break;
- }
- }
-
- if (usb3_1) {
- /* does xhci provide a PSI table for SSA speed attributes? */
- if (port_cap->psi_count) {
- /* two SSA entries for each unique PSI ID, RX and TX */
- ssa_count = port_cap->psi_uid_count * 2;
- ssa_size = ssa_count * sizeof(u32);
- ssp_cap_size -= 16; /* skip copying the default SSA */
- }
- desc_size += ssp_cap_size;
- }
- memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
-
- if (usb3_1) {
- /* modify bos descriptor bNumDeviceCaps and wTotalLength */
- buf[4] += 1;
- put_unaligned_le16(desc_size + ssa_size, &buf[2]);
- }
-
- if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
- return wLength;
-
- /* Indicate whether the host has LTM support. */
- temp = readl(&xhci->cap_regs->hcc_params);
- if (HCC_LTC(temp))
- buf[8] |= USB_LTM_SUPPORT;
-
- /* Set the U1 and U2 exit latencies. */
- if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
- temp = readl(&xhci->cap_regs->hcs_params3);
- buf[12] = HCS_U1_LATENCY(temp);
- put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
- }
-
- /* If PSI table exists, add the custom speed attributes from it */
- if (usb3_1 && port_cap->psi_count) {
- u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
- int offset;
-
- ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
-
- if (wLength < desc_size)
- return wLength;
- buf[ssp_cap_base] = ssp_cap_size + ssa_size;
-
- /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
- bm_attrib = (ssa_count - 1) & 0x1f;
- bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
- put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
-
- if (wLength < desc_size + ssa_size)
- return wLength;
- /*
- * Create the Sublink Speed Attributes (SSA) array.
- * The xhci PSI field and USB 3.1 SSA fields are very similar,
- * but link type bits 7:6 differ for values 01b and 10b.
- * xhci has also only one PSI entry for a symmetric link when
- * USB 3.1 requires two SSA entries (RX and TX) for every link
- */
- offset = desc_size;
- for (i = 0; i < port_cap->psi_count; i++) {
- psi = port_cap->psi[i];
- psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
- psi_exp = XHCI_EXT_PORT_PSIE(psi);
- psi_mant = XHCI_EXT_PORT_PSIM(psi);
-
- /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
- for (; psi_exp < 3; psi_exp++)
- psi_mant /= 1000;
- if (psi_mant >= 10)
- psi |= BIT(14);
-
- if ((psi & PLT_MASK) == PLT_SYM) {
- /* Symmetric, create SSA RX and TX from one PSI entry */
- put_unaligned_le32(psi, &buf[offset]);
- psi |= 1 << 7; /* turn entry to TX */
- offset += 4;
- if (offset >= desc_size + ssa_size)
- return desc_size + ssa_size;
- } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
- /* Asymetric RX, flip bits 7:6 for SSA */
- psi ^= PLT_MASK;
- }
- put_unaligned_le32(psi, &buf[offset]);
- offset += 4;
- if (offset >= desc_size + ssa_size)
- return desc_size + ssa_size;
- }
- }
- /* ssa_size is 0 for other than usb 3.1 hosts */
- return desc_size + ssa_size;
-}
-
static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
struct usb_hub_descriptor *desc, int ports)
{
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