static void xlp_pic_enable(struct irq_data *d)
{
unsigned long flags;
- struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
+ struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
BUG_ON(!pd);
spin_lock_irqsave(&pd->node->piclock, flags);
static void xlp_pic_disable(struct irq_data *d)
{
- struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
+ struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
unsigned long flags;
BUG_ON(!pd);
static void xlp_pic_mask_ack(struct irq_data *d)
{
- struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
+ struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
clear_c0_eimr(pd->picirq);
ack_c0_eirr(pd->picirq);
static void xlp_pic_unmask(struct irq_data *d)
{
- struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
+ struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
BUG_ON(!pd);
pic_data->picirq = picirq;
pic_data->node = nlm_get_node(node);
irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq);
- irq_set_handler_data(xirq, pic_data);
+ irq_set_chip_data(xirq, pic_data);
}
void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
int xirq;
xirq = nlm_irq_to_xirq(node, irq);
- pic_data = irq_get_handler_data(xirq);
+ pic_data = irq_get_chip_data(xirq);
if (WARN_ON(!pic_data))
return;
pic_data->extra_ack = xack;
*/
static void xlp_msi_enable(struct irq_data *d)
{
- struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+ struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
unsigned long flags;
int vec;
static void xlp_msi_disable(struct irq_data *d)
{
- struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+ struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
unsigned long flags;
int vec;
static void xlp_msi_mask_ack(struct irq_data *d)
{
- struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+ struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
int link, vec;
link = nlm_irq_msilink(d->irq);
msixvec = nlm_irq_msixvec(d->irq);
link = nlm_irq_msixlink(msixvec);
pci_msi_mask_irq(d);
- md = irq_data_get_irq_handler_data(d);
+ md = irq_data_get_irq_chip_data(d);
/* Ack MSI on bridge */
if (cpu_is_xlp9xx()) {
/* Get MSI data for the link */
lirq = PIC_PCIE_LINK_MSI_IRQ(link);
xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
- md = irq_get_handler_data(xirq);
+ md = irq_get_chip_data(xirq);
msiaddr = MSI_LINK_ADDR(node, link);
spin_lock_irqsave(&md->msi_lock, flags);
/* Get MSI data for the link */
lirq = PIC_PCIE_MSIX_IRQ(link);
xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
- md = irq_get_handler_data(xirq);
+ md = irq_get_chip_data(xirq);
msixaddr = MSIX_LINK_ADDR(node, link);
spin_lock_irqsave(&md->msi_lock, flags);
irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
- irq_set_handler_data(i, md);
+ irq_set_chip_data(i, md);
}
for (i = 0; i < XLP_MSIXVEC_PER_LINK ; i++) {
/* Initialize MSI-X extended irq space for the link */
irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
- irq_set_handler_data(irq, md);
+ irq_set_chip_data(irq, md);
}
}
link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
- md = irq_get_handler_data(irqbase);
+ md = irq_get_chip_data(irqbase);
if (cpu_is_xlp9xx())
status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
md->msi_enabled_mask;
link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
- md = irq_get_handler_data(irqbase);
+ md = irq_get_chip_data(irqbase);
if (cpu_is_xlp9xx())
status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
else