drm/amd/display: Updates for OTG and DCCG clocks

Use DTBCLK for valid pixel clock generation

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index df155cc2bfea09168137bfbdea7d04ab9f5f12cf..3fe5882ed01886aa224a055d642adfdb469a8c71 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -514,7 +514,6 @@ struct dcn_optc_registers {
        type DIG_UPDATE_POSITION_X;\
        type DIG_UPDATE_POSITION_Y;\
        type OTG_H_TIMING_DIV_MODE;\
-       type OTG_H_TIMING_DIV_MODE_MANUAL;\
        type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
        type OTG_CRC_DSC_MODE;\
        type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
@@ -522,13 +521,17 @@ struct dcn_optc_registers {
        type OTG_CRC_DATA_FORMAT;\
        type OTG_V_TOTAL_LAST_USED_BY_DRR;
 
+#define TG_REG_FIELD_LIST_DCN3_2(type) \
+       type OTG_H_TIMING_DIV_MODE_MANUAL;
 
 struct dcn_optc_shift {
        TG_REG_FIELD_LIST(uint8_t)
+       TG_REG_FIELD_LIST_DCN3_2(uint8_t)
 };
 
 struct dcn_optc_mask {
        TG_REG_FIELD_LIST(uint32_t)
+       TG_REG_FIELD_LIST_DCN3_2(uint32_t)
 };
 
 struct optc {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
index 0e54c0a105a10a5553d8224db8ee3fb4778da708..1c46fad0977bf34d402488a55d373358a01f49eb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
@@ -45,6 +45,7 @@
        SR(PHYDSYMCLK_CLOCK_CNTL),\
        SR(PHYESYMCLK_CLOCK_CNTL),\
        SR(DPSTREAMCLK_CNTL),\
+       SR(HDMISTREAMCLK_CNTL),\
        SR(SYMCLK32_SE_CNTL),\
        SR(SYMCLK32_LE_CNTL),\
        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
@@ -98,6 +99,8 @@
        DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
        DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
        DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
+       DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\
+       DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
        DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
        DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
        DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
@@ -143,6 +146,7 @@
        DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
        DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
        DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
+       DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
index e07b317ed3f45dde3fe104d419e29d6b9a9ed8fa..5e57c39235fab070ae7613080bb5b497944582b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -245,6 +245,7 @@
        SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
        SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
        SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
        SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
        SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)