s->regs[reg] = data;
aspeed_scu_set_apb_freq(s);
break;
-
+ case HW_STRAP1:
+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+ s->regs[HW_STRAP1] |= data;
+ return;
+ }
+ /* Jump to assignment below */
+ break;
+ case SILICON_REV:
+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+ s->regs[HW_STRAP1] &= ~data;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+ /* Avoid assignment below, we've handled everything */
+ return;
case FREQ_CNTR_EVAL:
case VGA_SCRATCH1 ... VGA_SCRATCH8:
case RNG_DATA:
- case SILICON_REV:
case FREE_CNTR4:
case FREE_CNTR4_EXT:
qemu_log_mask(LOG_GUEST_ERROR,
#define AST2500_A0_SILICON_REV 0x04000303U
#define AST2500_A1_SILICON_REV 0x04010303U
+#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
+
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define ASPEED_SCU_PROT_KEY 0x1688A8A8