drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelist

Required for WaAllowUMDToModifyHDCChicken1:skl,bxt

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: explain purpose of changes (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-4-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 511732ea0138c184dc59e2610541cc0e95aa794e..ed887cfc47f1cf58a5a6223ed433483933b1ab8f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6045,6 +6045,8 @@ enum skl_disp_power_wells {
 #define  HDC_FORCE_NON_COHERENT                        (1<<4)
 #define  HDC_BARRIER_PERFORMANCE_DISABLE       (1<<10)
 
+#define GEN8_HDC_CHICKEN1                      _MMIO(0x7304)
+
 /* GEN9 chicken */
 #define SLICE_ECO_CHICKEN0                     _MMIO(0x7308)
 #define   PIXEL_MASK_CAMMING_DISABLE           (1 << 14)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c938b93c4f83b457b6f0e9e86c23447abba105c2..62f535c1b78e1508a58f6dfa1c1fd71978dcaae8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -986,6 +986,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
        if (ret)
                return ret;
 
+       /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
+       ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1);
+       if (ret)
+               return ret;
+
        return 0;
 }