perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs

BugLink: https://bugs.launchpad.net/bugs/1839036
commit 2f217d58a8a086d3399fecce39fb358848e799c4 upstream.

Fill in the L3 performance event select register ThreadMask
bitfield, to enable per hardware thread accounting.

Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Gary Hook <Gary.Hook@amd.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Martin Liska <mliska@suse.cz>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: https://lkml.kernel.org/r/20190628215906.4276-2-kim.phillips@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 19caa458f226053d2dc334291197ead6604ec981..baa7e36073f907b19a983459aa15e66a682b9f95 100644 (file)
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -210,15 +210,22 @@ static int amd_uncore_event_init(struct perf_event *event)
        hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
        hwc->idx = -1;
 
+       if (event->cpu < 0)
+               return -EINVAL;
+
        /*
         * SliceMask and ThreadMask need to be set for certain L3 events in
         * Family 17h. For other events, the two fields do not affect the count.
         */
-       if (l3_mask && is_llc_event(event))
-               hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
+       if (l3_mask && is_llc_event(event)) {
+               int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4);
 
-       if (event->cpu < 0)
-               return -EINVAL;
+               if (smp_num_siblings > 1)
+                       thread += cpu_data(event->cpu).apicid & 1;
+
+               hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
+                               AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
+       }
 
        uncore = event_to_amd_uncore(event);
        if (!uncore)