struct at91_pinctrl_mux_ops *ops; /* ops */
};
-#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
-
static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
static int gpio_banks;
return -EINVAL;
}
chip = range->gc;
- at91_chip = container_of(chip, struct at91_gpio_chip, chip);
+ at91_chip = gpiochip_get_data(chip);
dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
u32 osr;
static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
u32 pdsr;
static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
int val)
{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
static void at91_gpio_set_multiple(struct gpio_chip *chip,
unsigned long *mask, unsigned long *bits)
{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int val)
{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
{
enum at91_mux mode;
int i;
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
for (i = 0; i < chip->ngpio; i++) {
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
- struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
- struct at91_gpio_chip, chip);
-
+ struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
void __iomem *pio = at91_gpio->regbase;
unsigned long isr;
int n;
return 0;
}
- prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip);
+ prev = gpiochip_get_data(gpiochip_prev);
/* we can only have 2 banks before */
for (i = 0; i < 2; i++) {
range->npins = chip->ngpio;
range->gc = chip;
- ret = gpiochip_add(chip);
+ ret = gpiochip_add_data(chip, at91_chip);
if (ret)
goto gpiochip_add_err;