KVM: SVM: Provide support for SEV-ES vCPU creation/loading

An SEV-ES vCPU requires additional VMCB initialization requirements for
vCPU creation and vCPU load/put requirements. This includes:

General VMCB initialization changes:
  - Set a VMCB control bit to enable SEV-ES support on the vCPU.
  - Set the VMCB encrypted VM save area address.
  - CRx registers are part of the encrypted register state and cannot be
    updated. Remove the CRx register read and write intercepts and replace
    them with CRx register write traps to track the CRx register values.
  - Certain MSR values are part of the encrypted register state and cannot
    be updated. Remove certain MSR intercepts (EFER, CR_PAT, etc.).
  - Remove the #GP intercept (no support for "enable_vmware_backdoor").
  - Remove the XSETBV intercept since the hypervisor cannot modify XCR0.

General vCPU creation changes:
  - Set the initial GHCB gpa value as per the GHCB specification.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <3a8aef366416eddd5556dfa3fdc212aafa1ad0a2.1607620209.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index caa8628f5fba6e49f713970d8b406bf7cbc27d1a..a57331de59e22aae5b7b43bd5828d7cbec28ec2f 100644 (file)
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -98,6 +98,16 @@ enum {
        INTERCEPT_MWAIT_COND,
        INTERCEPT_XSETBV,
        INTERCEPT_RDPRU,
+       TRAP_EFER_WRITE,
+       TRAP_CR0_WRITE,
+       TRAP_CR1_WRITE,
+       TRAP_CR2_WRITE,
+       TRAP_CR3_WRITE,
+       TRAP_CR4_WRITE,
+       TRAP_CR5_WRITE,
+       TRAP_CR6_WRITE,
+       TRAP_CR7_WRITE,
+       TRAP_CR8_WRITE,
        /* Byte offset 014h (word 5) */
        INTERCEPT_INVLPGB = 160,
        INTERCEPT_INVLPGB_ILLEGAL,
@@ -144,6 +154,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
        u8 reserved_6[8];       /* Offset 0xe8 */
        u64 avic_logical_id;    /* Offset 0xf0 */
        u64 avic_physical_id;   /* Offset 0xf8 */
+       u8 reserved_7[8];
+       u64 vmsa_pa;            /* Used for an SEV-ES guest */
 };
 
 
@@ -198,6 +210,7 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
 
 #define SVM_NESTED_CTL_NP_ENABLE       BIT(0)
 #define SVM_NESTED_CTL_SEV_ENABLE      BIT(1)
+#define SVM_NESTED_CTL_SEV_ES_ENABLE   BIT(2)
 
 struct vmcb_seg {
        u16 selector;
@@ -295,7 +308,7 @@ struct ghcb {
 
 
 #define EXPECTED_VMCB_SAVE_AREA_SIZE           1032
-#define EXPECTED_VMCB_CONTROL_AREA_SIZE                256
+#define EXPECTED_VMCB_CONTROL_AREA_SIZE                272
 #define EXPECTED_GHCB_SIZE                     PAGE_SIZE
 
 static inline void __unused_size_checks(void)

diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index b81d12f1bd37e2462224569f3e28a279ce5f8a17..584fede0b733f80f468833cbb74ffde87d07723c 100644 (file)
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -1796,3 +1796,59 @@ int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in)
        return kvm_sev_es_string_io(&svm->vcpu, size, port,
                                    svm->ghcb_sa, svm->ghcb_sa_len, in);
 }
+
+void sev_es_init_vmcb(struct vcpu_svm *svm)
+{
+       struct kvm_vcpu *vcpu = &svm->vcpu;
+
+       svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ES_ENABLE;
+       svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
+
+       /*
+        * An SEV-ES guest requires a VMSA area that is a separate from the
+        * VMCB page. Do not include the encryption mask on the VMSA physical
+        * address since hardware will access it using the guest key.
+        */
+       svm->vmcb->control.vmsa_pa = __pa(svm->vmsa);
+
+       /* Can't intercept CR register access, HV can't modify CR registers */
+       svm_clr_intercept(svm, INTERCEPT_CR0_READ);
+       svm_clr_intercept(svm, INTERCEPT_CR4_READ);
+       svm_clr_intercept(svm, INTERCEPT_CR8_READ);
+       svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
+       svm_clr_intercept(svm, INTERCEPT_CR4_WRITE);
+       svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
+
+       svm_clr_intercept(svm, INTERCEPT_SELECTIVE_CR0);
+
+       /* Track EFER/CR register changes */
+       svm_set_intercept(svm, TRAP_EFER_WRITE);
+       svm_set_intercept(svm, TRAP_CR0_WRITE);
+       svm_set_intercept(svm, TRAP_CR4_WRITE);
+       svm_set_intercept(svm, TRAP_CR8_WRITE);
+
+       /* No support for enable_vmware_backdoor */
+       clr_exception_intercept(svm, GP_VECTOR);
+
+       /* Can't intercept XSETBV, HV can't modify XCR0 directly */
+       svm_clr_intercept(svm, INTERCEPT_XSETBV);
+
+       /* Clear intercepts on selected MSRs */
+       set_msr_interception(vcpu, svm->msrpm, MSR_EFER, 1, 1);
+       set_msr_interception(vcpu, svm->msrpm, MSR_IA32_CR_PAT, 1, 1);
+       set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
+       set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
+       set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
+       set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
+}
+
+void sev_es_create_vcpu(struct vcpu_svm *svm)
+{
+       /*
+        * Set the GHCB MSR value as per the GHCB specification when creating
+        * a vCPU for an SEV-ES guest.
+        */
+       set_ghcb_msr(svm, GHCB_MSR_SEV_INFO(GHCB_VERSION_MAX,
+                                           GHCB_VERSION_MIN,
+                                           sev_enc_bit));
+}

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 4be7d13d4462b66194fd0a55f4a6143fc843b2d0..091f792498a25a8c6be39ee7bd8a362d4d24049d 100644 (file)
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -90,7 +90,7 @@ static DEFINE_PER_CPU(u64, current_tsc_ratio);
 
 static const struct svm_direct_access_msrs {
        u32 index;   /* Index of the MSR */
-       bool always; /* True if intercept is always on */
+       bool always; /* True if intercept is initially cleared */
 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
        { .index = MSR_STAR,                            .always = true  },
        { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
@@ -108,6 +108,9 @@ static const struct svm_direct_access_msrs {
        { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
        { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
        { .index = MSR_IA32_LASTINTTOIP,                .always = false },
+       { .index = MSR_EFER,                            .always = false },
+       { .index = MSR_IA32_CR_PAT,                     .always = false },
+       { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
        { .index = MSR_INVALID,                         .always = false },
 };
 
@@ -676,8 +679,8 @@ static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
        msrpm[offset] = tmp;
 }
 
-static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
-                                int read, int write)
+void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
+                         int read, int write)
 {
        set_shadow_msr_intercept(vcpu, msr, read, write);
        set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
@@ -1263,6 +1266,11 @@ static void init_vmcb(struct vcpu_svm *svm)
        if (sev_guest(svm->vcpu.kvm)) {
                svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
                clr_exception_intercept(svm, UD_VECTOR);
+
+               if (sev_es_guest(svm->vcpu.kvm)) {
+                       /* Perform SEV-ES specific VMCB updates */
+                       sev_es_init_vmcb(svm);
+               }
        }
 
        vmcb_mark_all_dirty(svm->vmcb);
@@ -1356,6 +1364,10 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu)
        svm_init_osvw(vcpu);
        vcpu->arch.microcode_version = 0x01000065;
 
+       if (sev_es_guest(svm->vcpu.kvm))
+               /* Perform SEV-ES specific VMCB creation updates */
+               sev_es_create_vcpu(svm);
+
        return 0;
 
 error_free_vmsa_page:
@@ -1451,6 +1463,7 @@ static void svm_vcpu_put(struct kvm_vcpu *vcpu)
        loadsegment(gs, svm->host.gs);
 #endif
 #endif
+
        for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
                wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 }
@@ -3101,6 +3114,7 @@ static void dump_vmcb(struct kvm_vcpu *vcpu)
        pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
        pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
        pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
+       pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
        pr_err("VMCB State Save Area:\n");
        pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
               "es:",

diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index b85c162a8a1e78bb7adad7e55a08157830fcdb66..03359185331c2b71df261053a2af58f7ed4d547f 100644 (file)
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -34,7 +34,7 @@ static const u32 host_save_user_msrs[] = {
 
 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 
-#define MAX_DIRECT_ACCESS_MSRS 15
+#define MAX_DIRECT_ACCESS_MSRS 18
 #define MSRPM_OFFSETS  16
 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 extern bool npt_enabled;
@@ -417,6 +417,8 @@ bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
 void svm_set_gif(struct vcpu_svm *svm, bool value);
 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code);
+void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
+                         int read, int write);
 
 /* nested.c */
 
@@ -576,5 +578,7 @@ void sev_hardware_teardown(void);
 void sev_free_vcpu(struct kvm_vcpu *vcpu);
 int sev_handle_vmgexit(struct vcpu_svm *svm);
 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
+void sev_es_init_vmcb(struct vcpu_svm *svm);
+void sev_es_create_vcpu(struct vcpu_svm *svm);
 
 #endif