L: qemu-arm@nongnu.org
S: Odd Fixes
F: hw/*/exynos*
-F: include/hw/arm/exynos4210.h
+F: include/hw/*/exynos*
Calxeda Highbank
M: Rob Herring <robh@kernel.org>
g_assert_not_reached();
}
-void QEMU_NORETURN cpu_loop_exit(CPUState *cpu)
+G_NORETURN void cpu_loop_exit(CPUState *cpu)
{
g_assert_not_reached();
}
-void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
+G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
{
g_assert_not_reached();
}
TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
target_ulong cs_base, uint32_t flags,
int cflags);
-
-void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
+G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
void page_init(void);
void tb_htable_init(void);
#include <sys/sysctl.h>
#include "qemu/osdep.h"
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qemu/units.h"
#include "qemu/accel.h"
#include "qemu-version.h"
}
/* Abort execution with signal. */
-static void QEMU_NORETURN dump_core_and_abort(int target_sig)
+static G_NORETURN
+void dump_core_and_abort(int target_sig)
{
CPUArchState *env = thread_cpu->env_ptr;
CPUState *cpu = env_cpu(env);
Automatic memory deallocation
=============================
-QEMU has a mandatory dependency either the GCC or CLang compiler. As
+QEMU has a mandatory dependency on either the GCC or the Clang compiler. As
such it has the freedom to make use of a C language extension for
automatically running a cleanup function when a stack variable goes
out of scope. This can be used to simplify function cleanup paths,
processed by the "tracetool" script to generate code for the trace events.
The individual "trace-events" files are merged into a "trace-events-all" file,
-which is also installed into "/usr/share/qemu" with the name "trace-events".
+which is also installed into "/usr/share/qemu".
This merged file is to be used by the "simpletrace.py" script to later analyse
traces in the simpletrace data format.
Valid values are:
``2``
- GICv2
+ GICv2. Note that this limits the number of CPUs to 8.
``3``
- GICv3
+ GICv3. This allows up to 512 CPUs.
``host``
Use the same GIC version the host provides, when using KVM
``max``
return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);
}
+static Int128 float128_to_int128_scalbn(float128 a, FloatRoundMode rmode,
+ int scale, float_status *s)
+{
+ int flags = 0;
+ Int128 r;
+ FloatParts128 p;
+
+ float128_unpack_canonical(&p, a, s);
+
+ switch (p.cls) {
+ case float_class_snan:
+ flags |= float_flag_invalid_snan;
+ /* fall through */
+ case float_class_qnan:
+ flags |= float_flag_invalid;
+ r = UINT128_MAX;
+ break;
+
+ case float_class_inf:
+ flags = float_flag_invalid | float_flag_invalid_cvti;
+ r = p.sign ? INT128_MIN : INT128_MAX;
+ break;
+
+ case float_class_zero:
+ return int128_zero();
+
+ case float_class_normal:
+ if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) {
+ flags = float_flag_inexact;
+ }
+
+ if (p.exp < 127) {
+ int shift = 127 - p.exp;
+ r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
+ if (p.sign) {
+ r = int128_neg(r);
+ }
+ } else if (p.exp == 127 && p.sign && p.frac_lo == 0 &&
+ p.frac_hi == DECOMPOSED_IMPLICIT_BIT) {
+ r = INT128_MIN;
+ } else {
+ flags = float_flag_invalid | float_flag_invalid_cvti;
+ r = p.sign ? INT128_MIN : INT128_MAX;
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ float_raise(flags, s);
+ return r;
+}
+
static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode,
int scale, float_status *s)
{
return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s);
}
+Int128 float128_to_int128(float128 a, float_status *s)
+{
+ return float128_to_int128_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
int32_t floatx80_to_int32(floatx80 a, float_status *s)
{
return floatx80_to_int32_scalbn(a, s->float_rounding_mode, 0, s);
return float128_to_int64_scalbn(a, float_round_to_zero, 0, s);
}
+Int128 float128_to_int128_round_to_zero(float128 a, float_status *s)
+{
+ return float128_to_int128_scalbn(a, float_round_to_zero, 0, s);
+}
+
int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *s)
{
return floatx80_to_int32_scalbn(a, float_round_to_zero, 0, s);
return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s);
}
+static Int128 float128_to_uint128_scalbn(float128 a, FloatRoundMode rmode,
+ int scale, float_status *s)
+{
+ int flags = 0;
+ Int128 r;
+ FloatParts128 p;
+
+ float128_unpack_canonical(&p, a, s);
+
+ switch (p.cls) {
+ case float_class_snan:
+ flags |= float_flag_invalid_snan;
+ /* fall through */
+ case float_class_qnan:
+ flags |= float_flag_invalid;
+ r = UINT128_MAX;
+ break;
+
+ case float_class_inf:
+ flags = float_flag_invalid | float_flag_invalid_cvti;
+ r = p.sign ? int128_zero() : UINT128_MAX;
+ break;
+
+ case float_class_zero:
+ return int128_zero();
+
+ case float_class_normal:
+ if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) {
+ flags = float_flag_inexact;
+ if (p.cls == float_class_zero) {
+ r = int128_zero();
+ break;
+ }
+ }
+
+ if (p.sign) {
+ flags = float_flag_invalid | float_flag_invalid_cvti;
+ r = int128_zero();
+ } else if (p.exp <= 127) {
+ int shift = 127 - p.exp;
+ r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
+ } else {
+ flags = float_flag_invalid | float_flag_invalid_cvti;
+ r = UINT128_MAX;
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ float_raise(flags, s);
+ return r;
+}
+
uint8_t float16_to_uint8(float16 a, float_status *s)
{
return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s);
return float128_to_uint64_scalbn(a, s->float_rounding_mode, 0, s);
}
+Int128 float128_to_uint128(float128 a, float_status *s)
+{
+ return float128_to_uint128_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
uint16_t float16_to_uint16_round_to_zero(float16 a, float_status *s)
{
return float16_to_uint16_scalbn(a, float_round_to_zero, 0, s);
return float128_to_uint64_scalbn(a, float_round_to_zero, 0, s);
}
+Int128 float128_to_uint128_round_to_zero(float128 a, float_status *s)
+{
+ return float128_to_uint128_scalbn(a, float_round_to_zero, 0, s);
+}
+
uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s)
{
return bfloat16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s);
return int64_to_bfloat16_scalbn(a, 0, status);
}
+float128 int128_to_float128(Int128 a, float_status *status)
+{
+ FloatParts128 p = { };
+ int shift;
+
+ if (int128_nz(a)) {
+ p.cls = float_class_normal;
+ if (!int128_nonneg(a)) {
+ p.sign = true;
+ a = int128_neg(a);
+ }
+
+ shift = clz64(int128_gethi(a));
+ if (shift == 64) {
+ shift += clz64(int128_getlo(a));
+ }
+
+ p.exp = 127 - shift;
+ a = int128_lshift(a, shift);
+
+ p.frac_hi = int128_gethi(a);
+ p.frac_lo = int128_getlo(a);
+ } else {
+ p.cls = float_class_zero;
+ }
+
+ return float128_round_pack_canonical(&p, status);
+}
+
float128 int64_to_float128(int64_t a, float_status *status)
{
FloatParts128 p;
return float128_round_pack_canonical(&p, status);
}
+float128 uint128_to_float128(Int128 a, float_status *status)
+{
+ FloatParts128 p = { };
+ int shift;
+
+ if (int128_nz(a)) {
+ p.cls = float_class_normal;
+
+ shift = clz64(int128_gethi(a));
+ if (shift == 64) {
+ shift += clz64(int128_getlo(a));
+ }
+
+ p.exp = 127 - shift;
+ a = int128_lshift(a, shift);
+
+ p.frac_hi = int128_gethi(a);
+ p.frac_lo = int128_getlo(a);
+ } else {
+ p.cls = float_class_zero;
+ }
+
+ return float128_round_pack_canonical(&p, status);
+}
+
/*
* Minimum and maximum
*/
int i;
for (i = 0; i < AW_A10_NUM_USB; i++) {
- char bus[16];
-
- sprintf(bus, "usb-bus.%d", i);
+ g_autofree char *bus = g_strdup_printf("usb-bus.%d", i);
object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
true, &error_fatal);
object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
-#define DIGIC_TIMER_NAME_MLEN 11
- char name[DIGIC_TIMER_NAME_MLEN];
-
- snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
+ g_autofree char *name = g_strdup_printf("timer[%d]", i);
object_initialize_child(obj, name, &s->timer[i], TYPE_DIGIC_TIMER);
}
#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
+enum ExtGicId {
+ EXT_GIC_ID_MDMA_LCD0 = 66,
+ EXT_GIC_ID_PDMA0,
+ EXT_GIC_ID_PDMA1,
+ EXT_GIC_ID_TIMER0,
+ EXT_GIC_ID_TIMER1,
+ EXT_GIC_ID_TIMER2,
+ EXT_GIC_ID_TIMER3,
+ EXT_GIC_ID_TIMER4,
+ EXT_GIC_ID_MCT_L0,
+ EXT_GIC_ID_WDT,
+ EXT_GIC_ID_RTC_ALARM,
+ EXT_GIC_ID_RTC_TIC,
+ EXT_GIC_ID_GPIO_XB,
+ EXT_GIC_ID_GPIO_XA,
+ EXT_GIC_ID_MCT_L1,
+ EXT_GIC_ID_IEM_APC,
+ EXT_GIC_ID_IEM_IEC,
+ EXT_GIC_ID_NFC,
+ EXT_GIC_ID_UART0,
+ EXT_GIC_ID_UART1,
+ EXT_GIC_ID_UART2,
+ EXT_GIC_ID_UART3,
+ EXT_GIC_ID_UART4,
+ EXT_GIC_ID_MCT_G0,
+ EXT_GIC_ID_I2C0,
+ EXT_GIC_ID_I2C1,
+ EXT_GIC_ID_I2C2,
+ EXT_GIC_ID_I2C3,
+ EXT_GIC_ID_I2C4,
+ EXT_GIC_ID_I2C5,
+ EXT_GIC_ID_I2C6,
+ EXT_GIC_ID_I2C7,
+ EXT_GIC_ID_SPI0,
+ EXT_GIC_ID_SPI1,
+ EXT_GIC_ID_SPI2,
+ EXT_GIC_ID_MCT_G1,
+ EXT_GIC_ID_USB_HOST,
+ EXT_GIC_ID_USB_DEVICE,
+ EXT_GIC_ID_MODEMIF,
+ EXT_GIC_ID_HSMMC0,
+ EXT_GIC_ID_HSMMC1,
+ EXT_GIC_ID_HSMMC2,
+ EXT_GIC_ID_HSMMC3,
+ EXT_GIC_ID_SDMMC,
+ EXT_GIC_ID_MIPI_CSI_4LANE,
+ EXT_GIC_ID_MIPI_DSI_4LANE,
+ EXT_GIC_ID_MIPI_CSI_2LANE,
+ EXT_GIC_ID_MIPI_DSI_2LANE,
+ EXT_GIC_ID_ONENAND_AUDI,
+ EXT_GIC_ID_ROTATOR,
+ EXT_GIC_ID_FIMC0,
+ EXT_GIC_ID_FIMC1,
+ EXT_GIC_ID_FIMC2,
+ EXT_GIC_ID_FIMC3,
+ EXT_GIC_ID_JPEG,
+ EXT_GIC_ID_2D,
+ EXT_GIC_ID_PCIe,
+ EXT_GIC_ID_MIXER,
+ EXT_GIC_ID_HDMI,
+ EXT_GIC_ID_HDMI_I2C,
+ EXT_GIC_ID_MFC,
+ EXT_GIC_ID_TVENC,
+};
+
+enum ExtInt {
+ EXT_GIC_ID_EXTINT0 = 48,
+ EXT_GIC_ID_EXTINT1,
+ EXT_GIC_ID_EXTINT2,
+ EXT_GIC_ID_EXTINT3,
+ EXT_GIC_ID_EXTINT4,
+ EXT_GIC_ID_EXTINT5,
+ EXT_GIC_ID_EXTINT6,
+ EXT_GIC_ID_EXTINT7,
+ EXT_GIC_ID_EXTINT8,
+ EXT_GIC_ID_EXTINT9,
+ EXT_GIC_ID_EXTINT10,
+ EXT_GIC_ID_EXTINT11,
+ EXT_GIC_ID_EXTINT12,
+ EXT_GIC_ID_EXTINT13,
+ EXT_GIC_ID_EXTINT14,
+ EXT_GIC_ID_EXTINT15
+};
+
+/*
+ * External GIC sources which are not from External Interrupt Combiner or
+ * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
+ * which is INTG16 in Internal Interrupt Combiner.
+ */
+
+static const uint32_t
+combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+ /* int combiner groups 16-19 */
+ { }, { }, { }, { },
+ /* int combiner group 20 */
+ { 0, EXT_GIC_ID_MDMA_LCD0 },
+ /* int combiner group 21 */
+ { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
+ /* int combiner group 22 */
+ { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
+ EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
+ /* int combiner group 23 */
+ { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
+ /* int combiner group 24 */
+ { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
+ /* int combiner group 25 */
+ { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
+ /* int combiner group 26 */
+ { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
+ EXT_GIC_ID_UART4 },
+ /* int combiner group 27 */
+ { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
+ EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
+ EXT_GIC_ID_I2C7 },
+ /* int combiner group 28 */
+ { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
+ /* int combiner group 29 */
+ { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
+ EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
+ /* int combiner group 30 */
+ { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
+ /* int combiner group 31 */
+ { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
+ /* int combiner group 32 */
+ { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
+ /* int combiner group 33 */
+ { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
+ /* int combiner group 34 */
+ { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+ /* int combiner group 35 */
+ { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
+ /* int combiner group 36 */
+ { EXT_GIC_ID_MIXER },
+ /* int combiner group 37 */
+ { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
+ EXT_GIC_ID_EXTINT7 },
+ /* groups 38-50 */
+ { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+ /* int combiner group 51 */
+ { EXT_GIC_ID_MCT_L0 },
+ /* group 52 */
+ { },
+ /* int combiner group 53 */
+ { EXT_GIC_ID_WDT },
+ /* groups 54-63 */
+ { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+};
+
+#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit))
+#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
+#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
+ ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
+
+/*
+ * Some interrupt lines go to multiple combiner inputs.
+ * This data structure defines those: each array element is
+ * a list of combiner inputs which are connected together;
+ * the one with the smallest interrupt ID value must be first.
+ * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
+ * wired to anything so we can use 0 as a terminator.
+ */
+#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
+#define IRQNONE 0
+
+#define COMBINERMAP_SIZE 16
+
+static const int combinermap[COMBINERMAP_SIZE][6] = {
+ /* MDNIE_LCD1 */
+ { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
+ { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
+ { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
+ { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
+ /* TMU */
+ { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
+ { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
+ { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
+ { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
+ /* LCD1 */
+ { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
+ { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
+ { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
+ { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
+ /* Multi-core timer */
+ { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
+ { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
+ { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
+ { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
+};
+
+#undef IRQNO
+
+static const int *combinermap_entry(int irq)
+{
+ /*
+ * If the interrupt number passed in is the first entry in some
+ * line of the combinermap, return a pointer to that line;
+ * otherwise return NULL.
+ */
+ int i;
+ for (i = 0; i < COMBINERMAP_SIZE; i++) {
+ if (combinermap[i][0] == irq) {
+ return combinermap[i];
+ }
+ }
+ return NULL;
+}
+
+static int mapline_size(const int *mapline)
+{
+ /* Return number of entries in this mapline in total */
+ int i = 0;
+
+ if (!mapline) {
+ /* Not in the map? IRQ goes to exactly one combiner input */
+ return 1;
+ }
+ while (*mapline != IRQNONE) {
+ mapline++;
+ i++;
+ }
+ return i;
+}
+
+/*
+ * Initialize board IRQs.
+ * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+ */
+static void exynos4210_init_board_irqs(Exynos4210State *s)
+{
+ uint32_t grp, bit, irq_id, n;
+ DeviceState *extgicdev = DEVICE(&s->ext_gic);
+ DeviceState *intcdev = DEVICE(&s->int_combiner);
+ DeviceState *extcdev = DEVICE(&s->ext_combiner);
+ int splitcount = 0;
+ DeviceState *splitter;
+ const int *mapline;
+ int numlines, splitin, in;
+
+ for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+ irq_id = 0;
+ if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
+ /* MCT_G0 is passed to External GIC */
+ irq_id = EXT_GIC_ID_MCT_G0;
+ }
+ if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
+ /* MCT_G1 is passed to External and GIC */
+ irq_id = EXT_GIC_ID_MCT_G1;
+ }
+
+ if (s->irq_table[n]) {
+ /*
+ * This must be some non-first entry in a combinermap line,
+ * and we've already filled it in.
+ */
+ continue;
+ }
+ mapline = combinermap_entry(n);
+ /*
+ * We need to connect the IRQ to multiple inputs on both combiners
+ * and possibly also to the external GIC.
+ */
+ numlines = 2 * mapline_size(mapline);
+ if (irq_id) {
+ numlines++;
+ }
+ assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+ splitter = DEVICE(&s->splitter[splitcount]);
+ qdev_prop_set_uint16(splitter, "num-lines", numlines);
+ qdev_realize(splitter, NULL, &error_abort);
+ splitcount++;
+
+ in = n;
+ splitin = 0;
+ for (;;) {
+ s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
+ qdev_connect_gpio_out(splitter, splitin,
+ qdev_get_gpio_in(intcdev, in));
+ qdev_connect_gpio_out(splitter, splitin + 1,
+ qdev_get_gpio_in(extcdev, in));
+ splitin += 2;
+ if (!mapline) {
+ break;
+ }
+ mapline++;
+ in = *mapline;
+ if (in == IRQNONE) {
+ break;
+ }
+ }
+ if (irq_id) {
+ qdev_connect_gpio_out(splitter, splitin,
+ qdev_get_gpio_in(extgicdev, irq_id - 32));
+ }
+ }
+ for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+ /* these IDs are passed to Internal Combiner and External GIC */
+ grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
+ bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+ irq_id = combiner_grp_to_gic_id[grp -
+ EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+
+ if (s->irq_table[n]) {
+ /*
+ * This must be some non-first entry in a combinermap line,
+ * and we've already filled it in.
+ */
+ continue;
+ }
+
+ if (irq_id) {
+ assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+ splitter = DEVICE(&s->splitter[splitcount]);
+ qdev_prop_set_uint16(splitter, "num-lines", 2);
+ qdev_realize(splitter, NULL, &error_abort);
+ splitcount++;
+ s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+ qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
+ qdev_connect_gpio_out(splitter, 1,
+ qdev_get_gpio_in(extgicdev, irq_id - 32));
+ } else {
+ s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
+ }
+ }
+ /*
+ * We check this here to avoid a more obscure assert later when
+ * qdev_assert_realized_properly() checks that we realized every
+ * child object we initialized.
+ */
+ assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
+}
+
+/*
+ * Get IRQ number from exynos4210 IRQ subsystem stub.
+ * To identify IRQ source use internal combiner group and bit number
+ * grp - group number
+ * bit - bit number inside group
+ */
+uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+{
+ return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+}
+
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
0x09, 0x00, 0x00, 0x00 };
{
Exynos4210State *s = EXYNOS4210_SOC(socdev);
MemoryRegion *system_mem = get_system_memory();
- qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
SysBusDevice *busdev;
DeviceState *dev, *uart[4], *pl330[3];
int i, n;
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
}
- /*** IRQs ***/
-
- s->irq_table = exynos4210_init_irq(&s->irqs);
-
/* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
- dev = qdev_new("exynos4210.irq_gate");
- qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- /* Get IRQ Gate input in gate_irq */
- for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
- gate_irq[i][n] = qdev_get_gpio_in(dev, n);
- }
- busdev = SYS_BUS_DEVICE(dev);
-
- /* Connect IRQ Gate output to CPU's IRQ line */
- sysbus_connect_irq(busdev, 0,
- qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
+ DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
+ object_property_set_int(OBJECT(orgate), "num-lines",
+ EXYNOS4210_IRQ_GATE_NINPUTS,
+ &error_abort);
+ qdev_realize(orgate, NULL, &error_abort);
+ qdev_connect_gpio_out(orgate, 0,
+ qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
}
/* Private memory region and Internal GIC */
- dev = qdev_new(TYPE_A9MPCORE_PRIV);
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- busdev = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(busdev, &error_fatal);
+ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
+ busdev = SYS_BUS_DEVICE(&s->a9mpcore);
+ sysbus_realize(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- sysbus_connect_irq(busdev, n, gate_irq[n][0]);
- }
- for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
- s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+ sysbus_connect_irq(busdev, n,
+ qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
}
/* Cache controller */
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
/* External GIC */
- dev = qdev_new("exynos4210.gic");
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- busdev = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(busdev, &error_fatal);
+ qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
+ busdev = SYS_BUS_DEVICE(&s->ext_gic);
+ sysbus_realize(busdev, &error_fatal);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
/* Map Distributer interface */
sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- sysbus_connect_irq(busdev, n, gate_irq[n][1]);
- }
- for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
- s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
+ sysbus_connect_irq(busdev, n,
+ qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
}
/* Internal Interrupt Combiner */
- dev = qdev_new("exynos4210.combiner");
- busdev = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(busdev, &error_fatal);
+ busdev = SYS_BUS_DEVICE(&s->int_combiner);
+ sysbus_realize(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
- sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
+ sysbus_connect_irq(busdev, n,
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
}
- exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
/* External Interrupt Combiner */
- dev = qdev_new("exynos4210.combiner");
- qdev_prop_set_uint32(dev, "external", 1);
- busdev = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(busdev, &error_fatal);
+ qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
+ busdev = SYS_BUS_DEVICE(&s->ext_combiner);
+ sysbus_realize(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
- sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
+ sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
}
- exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
/* Initialize board IRQs. */
- exynos4210_init_board_irqs(&s->irqs);
+ exynos4210_init_board_irqs(s);
/*** Memory ***/
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
g_free(name);
}
+
+ for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
+ g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
+ object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
+ g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
+ object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
+ }
+
+ object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+ object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
+ object_initialize_child(obj, "int-combiner", &s->int_combiner,
+ TYPE_EXYNOS4210_COMBINER);
+ object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
+ TYPE_EXYNOS4210_COMBINER);
}
static void exynos4210_class_init(ObjectClass *klass, void *data)
#include "sysemu/sysemu.h"
#include "sysemu/block-backend.h"
-#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
-#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
-#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
-#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
-#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
+#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \
+ NPCM7XX_PWRON_STRAP_SPI0F18 | \
+ NPCM7XX_PWRON_STRAP_SFAB | \
+ NPCM7XX_PWRON_STRAP_BSPA | \
+ NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \
+ NPCM7XX_PWRON_STRAP_SECEN | \
+ NPCM7XX_PWRON_STRAP_HIZ | \
+ NPCM7XX_PWRON_STRAP_ECC | \
+ NPCM7XX_PWRON_STRAP_RESERVE1 | \
+ NPCM7XX_PWRON_STRAP_J2EN | \
+ NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
+
+#define NPCM750_EVB_POWER_ON_STRAPS ( \
+ NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
+#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define QUANTA_GBS_POWER_ON_STRAPS ( \
+ NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
+#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
+#include "hw/core/split-irq.h"
#include "hw/net/lan9118.h"
#include "hw/net/smc91c111.h"
#include "hw/pci/pci.h"
+#include "hw/qdev-core.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
0x76d
};
+static void split_irq_from_named(DeviceState *src, const char* outname,
+ qemu_irq out1, qemu_irq out2) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+
+ qdev_prop_set_uint32(splitter, "num-lines", 2);
+
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+
+ qdev_connect_gpio_out(splitter, 0, out1);
+ qdev_connect_gpio_out(splitter, 1, out2);
+ qdev_connect_gpio_out_named(src, outname, 0,
+ qdev_get_gpio_in(splitter, 0));
+}
+
static void realview_init(MachineState *machine,
enum realview_board_type board_type)
{
DeviceState *dev, *sysctl, *gpio2, *pl041;
SysBusDevice *busdev;
qemu_irq pic[64];
- qemu_irq mmc_irq[2];
PCIBus *pci_bus = NULL;
NICInfo *nd;
DriveInfo *dinfo;
* and the PL061 has them the other way about. Also the card
* detect line is inverted.
*/
- mmc_irq[0] = qemu_irq_split(
- qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
- qdev_get_gpio_in(gpio2, 1));
- mmc_irq[1] = qemu_irq_split(
- qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
- qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
- qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]);
- qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]);
+ split_irq_from_named(dev, "card-read-only",
+ qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
+ qdev_get_gpio_in(gpio2, 1));
+
+ split_irq_from_named(dev, "card-inserted",
+ qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
+ qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
+
dinfo = drive_get(IF_SD, 0, 0);
if (dinfo) {
DeviceState *card;
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "hw/core/split-irq.h"
#include "hw/sysbus.h"
#include "hw/sd/sd.h"
#include "hw/ssi/ssi.h"
DeviceState *ssddev;
DriveInfo *dinfo;
DeviceState *carddev;
+ DeviceState *gpio_d_splitter;
BlockBackend *blk;
/*
&error_fatal);
ssddev = ssi_create_peripheral(bus, "ssd0323");
- gpio_out[GPIO_D][0] = qemu_irq_split(
- qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
+
+ gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
+ qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
+ qdev_connect_gpio_out(
+ gpio_d_splitter, 0,
+ qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
+ qdev_connect_gpio_out(
+ gpio_d_splitter, 1,
qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
+ gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
+
gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
/* Make sure the select pin is high. */
exit(1);
}
+ if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+ error_report("mach-virt: %s does not support providing "
+ "Security extensions (TrustZone) to the guest CPU",
+ kvm_enabled() ? "KVM" : "HVF");
+ exit(1);
+ }
+
if (vms->virt && (kvm_enabled() || hvf_enabled())) {
error_report("mach-virt: %s does not support providing "
"Virtualization extensions to the guest CPU",
mc->desc = "Xilinx Versal Virtual development board";
mc->init = versal_virt_init;
- mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
- mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
- mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
+ mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+ mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+ mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
mc->no_cdrom = true;
mc->default_ram_id = "ddr";
}
#include "hw/sysbus.h"
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
+#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
#define GEM_REVISION 0x40070106
#define VERSAL_NUM_PMC_APB_IRQS 3
{
int i;
+ object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
+ TYPE_CPU_CLUSTER);
+ qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
+
for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
Object *obj;
- object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
+ object_initialize_child(OBJECT(&s->fpd.apu.cluster),
+ "apu-cpu[*]", &s->fpd.apu.cpu[i],
XLNX_VERSAL_ACPU_TYPE);
obj = OBJECT(&s->fpd.apu.cpu[i]);
if (i) {
&error_abort);
qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
+
+ qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
}
static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
}
}
+static void versal_create_rpu_cpus(Versal *s)
+{
+ int i;
+
+ object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
+ TYPE_CPU_CLUSTER);
+ qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
+ Object *obj;
+
+ object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
+ "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
+ XLNX_VERSAL_RCPU_TYPE);
+ obj = OBJECT(&s->lpd.rpu.cpu[i]);
+ object_property_set_bool(obj, "start-powered-off", true,
+ &error_abort);
+
+ object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
+ object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
+ &error_abort);
+ object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
+ &error_abort);
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
+ }
+
+ qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
+}
+
static void versal_create_uarts(Versal *s, qemu_irq *pic)
{
int i;
qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
}
+static void versal_create_crl(Versal *s, qemu_irq *pic)
+{
+ SysBusDevice *sbd;
+ int i;
+
+ object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
+ TYPE_XLNX_VERSAL_CRL);
+ sbd = SYS_BUS_DEVICE(&s->lpd.crl);
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
+ g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
+
+ object_property_set_link(OBJECT(&s->lpd.crl),
+ name, OBJECT(&s->lpd.rpu.cpu[i]),
+ &error_abort);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
+ g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
+
+ object_property_set_link(OBJECT(&s->lpd.crl),
+ name, OBJECT(&s->lpd.iou.gem[i]),
+ &error_abort);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
+ g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
+
+ object_property_set_link(OBJECT(&s->lpd.crl),
+ name, OBJECT(&s->lpd.iou.adma[i]),
+ &error_abort);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
+ g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
+
+ object_property_set_link(OBJECT(&s->lpd.crl),
+ name, OBJECT(&s->lpd.iou.uart[i]),
+ &error_abort);
+ }
+
+ object_property_set_link(OBJECT(&s->lpd.crl),
+ "usb", OBJECT(&s->lpd.iou.usb),
+ &error_abort);
+
+ sysbus_realize(sbd, &error_fatal);
+ memory_region_add_subregion(&s->mr_ps, MM_CRL,
+ sysbus_mmio_get_region(sbd, 0));
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
versal_unimp_area(s, "psm", &s->mr_ps,
MM_PSM_START, MM_PSM_END - MM_PSM_START);
- versal_unimp_area(s, "crl", &s->mr_ps,
- MM_CRL, MM_CRL_SIZE);
versal_unimp_area(s, "crf", &s->mr_ps,
MM_FPD_CRF, MM_FPD_CRF_SIZE);
versal_unimp_area(s, "apu", &s->mr_ps,
versal_create_apu_cpus(s);
versal_create_apu_gic(s, pic);
+ versal_create_rpu_cpus(s);
versal_create_uarts(s, pic);
versal_create_usbs(s, pic);
versal_create_gems(s, pic);
versal_create_efuse(s, pic);
versal_create_pmc_iou_slcr(s, pic);
versal_create_ospi(s, pic);
+ versal_create_crl(s, pic);
versal_map_ddr(s);
versal_unimp(s);
memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
+ memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
+ &s->lpd.rpu.mr_ps_alias, 0);
}
static void versal_init(Object *obj)
Versal *s = XLNX_VERSAL(obj);
memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
+ memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
+ memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
+ "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
}
static Property versal_properties[] = {
#define APU_ADDR 0xfd5c0000
#define APU_IRQ 153
+#define TTC0_ADDR 0xFF110000
+#define TTC0_IRQ 36
+
#define IPI_ADDR 0xFF300000
#define IPI_IRQ 64
sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
}
+static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+ int i, irq;
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
+ object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
+ TYPE_CADENCE_TTC);
+ sbd = SYS_BUS_DEVICE(&s->ttc[i]);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
+ for (irq = 0; irq < 3; irq++) {
+ sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
+ }
+ }
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
xlnx_zynqmp_create_efuse(s, gic_spi);
xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
xlnx_zynqmp_create_crf(s, gic_spi);
+ xlnx_zynqmp_create_ttc(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
return qemu_allocate_irq(qemu_notirq, irq, 0);
}
-static void qemu_splitirq(void *opaque, int line, int level)
-{
- struct IRQState **irq = opaque;
- irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
- irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
-}
-
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
-{
- qemu_irq *s = g_new0(qemu_irq, 2);
- s[0] = irq1;
- s[1] = irq2;
- return qemu_allocate_irq(qemu_splitirq, s, 0);
-}
-
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
{
int i;
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "qemu/sockets.h"
-#include "qemu-common.h"
#include "qapi/error.h"
#include "migration/vmstate.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
-
+#include "hw/intc/exynos4210_combiner.h"
#include "hw/arm/exynos4210.h"
#include "hw/hw.h"
#include "hw/irq.h"
#define DPRINTF(fmt, ...) do {} while (0)
#endif
-#define IIC_NGRP 64 /* Internal Interrupt Combiner
- Groups number */
-#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner
- Interrupts number */
#define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */
-#define IIC_REGSET_SIZE 0x41
-
-/*
- * State for each output signal of internal combiner
- */
-typedef struct CombinerGroupState {
- uint8_t src_mask; /* 1 - source enabled, 0 - disabled */
- uint8_t src_pending; /* Pending source interrupts before masking */
-} CombinerGroupState;
-
-#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
-
-struct Exynos4210CombinerState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
-
- struct CombinerGroupState group[IIC_NGRP];
- uint32_t reg_set[IIC_REGSET_SIZE];
- uint32_t icipsr[2];
- uint32_t external; /* 1 means that this combiner is external */
-
- qemu_irq output_irq[IIC_NGRP];
-};
static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
.name = "exynos4210.combiner.groupstate",
}
};
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
- int ext)
-{
- int n;
- int bit;
- int max;
- qemu_irq *irq;
-
- max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
- EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
- irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
-
- /*
- * Some IRQs of Int/External Combiner are going to two Combiners groups,
- * so let split them.
- */
- for (n = 0; n < max; n++) {
-
- bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-
- switch (n) {
- /* MDNIE_LCD1 INTG1 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
- EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
- continue;
-
- /* TMU INTG3 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
- continue;
-
- /* LCD1 INTG12 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
- EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
- continue;
-
- /* Multi-Core Timer INTG12 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
- EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
- continue;
-
- /* Multi-Core Timer INTG35 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
- EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
- continue;
-
- /* Multi-Core Timer INTG51 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
- EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
- continue;
-
- /* Multi-Core Timer INTG53 */
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
- EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
- continue;
- }
-
- irq[n] = qdev_get_gpio_in(dev, n);
- }
-}
-
static uint64_t
exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
{
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "hw/intc/exynos4210_gic.h"
#include "hw/arm/exynos4210.h"
#include "qom/object.h"
-enum ExtGicId {
- EXT_GIC_ID_MDMA_LCD0 = 66,
- EXT_GIC_ID_PDMA0,
- EXT_GIC_ID_PDMA1,
- EXT_GIC_ID_TIMER0,
- EXT_GIC_ID_TIMER1,
- EXT_GIC_ID_TIMER2,
- EXT_GIC_ID_TIMER3,
- EXT_GIC_ID_TIMER4,
- EXT_GIC_ID_MCT_L0,
- EXT_GIC_ID_WDT,
- EXT_GIC_ID_RTC_ALARM,
- EXT_GIC_ID_RTC_TIC,
- EXT_GIC_ID_GPIO_XB,
- EXT_GIC_ID_GPIO_XA,
- EXT_GIC_ID_MCT_L1,
- EXT_GIC_ID_IEM_APC,
- EXT_GIC_ID_IEM_IEC,
- EXT_GIC_ID_NFC,
- EXT_GIC_ID_UART0,
- EXT_GIC_ID_UART1,
- EXT_GIC_ID_UART2,
- EXT_GIC_ID_UART3,
- EXT_GIC_ID_UART4,
- EXT_GIC_ID_MCT_G0,
- EXT_GIC_ID_I2C0,
- EXT_GIC_ID_I2C1,
- EXT_GIC_ID_I2C2,
- EXT_GIC_ID_I2C3,
- EXT_GIC_ID_I2C4,
- EXT_GIC_ID_I2C5,
- EXT_GIC_ID_I2C6,
- EXT_GIC_ID_I2C7,
- EXT_GIC_ID_SPI0,
- EXT_GIC_ID_SPI1,
- EXT_GIC_ID_SPI2,
- EXT_GIC_ID_MCT_G1,
- EXT_GIC_ID_USB_HOST,
- EXT_GIC_ID_USB_DEVICE,
- EXT_GIC_ID_MODEMIF,
- EXT_GIC_ID_HSMMC0,
- EXT_GIC_ID_HSMMC1,
- EXT_GIC_ID_HSMMC2,
- EXT_GIC_ID_HSMMC3,
- EXT_GIC_ID_SDMMC,
- EXT_GIC_ID_MIPI_CSI_4LANE,
- EXT_GIC_ID_MIPI_DSI_4LANE,
- EXT_GIC_ID_MIPI_CSI_2LANE,
- EXT_GIC_ID_MIPI_DSI_2LANE,
- EXT_GIC_ID_ONENAND_AUDI,
- EXT_GIC_ID_ROTATOR,
- EXT_GIC_ID_FIMC0,
- EXT_GIC_ID_FIMC1,
- EXT_GIC_ID_FIMC2,
- EXT_GIC_ID_FIMC3,
- EXT_GIC_ID_JPEG,
- EXT_GIC_ID_2D,
- EXT_GIC_ID_PCIe,
- EXT_GIC_ID_MIXER,
- EXT_GIC_ID_HDMI,
- EXT_GIC_ID_HDMI_I2C,
- EXT_GIC_ID_MFC,
- EXT_GIC_ID_TVENC,
-};
-
-enum ExtInt {
- EXT_GIC_ID_EXTINT0 = 48,
- EXT_GIC_ID_EXTINT1,
- EXT_GIC_ID_EXTINT2,
- EXT_GIC_ID_EXTINT3,
- EXT_GIC_ID_EXTINT4,
- EXT_GIC_ID_EXTINT5,
- EXT_GIC_ID_EXTINT6,
- EXT_GIC_ID_EXTINT7,
- EXT_GIC_ID_EXTINT8,
- EXT_GIC_ID_EXTINT9,
- EXT_GIC_ID_EXTINT10,
- EXT_GIC_ID_EXTINT11,
- EXT_GIC_ID_EXTINT12,
- EXT_GIC_ID_EXTINT13,
- EXT_GIC_ID_EXTINT14,
- EXT_GIC_ID_EXTINT15
-};
-
-/*
- * External GIC sources which are not from External Interrupt Combiner or
- * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
- * which is INTG16 in Internal Interrupt Combiner.
- */
-
-static const uint32_t
-combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
- /* int combiner groups 16-19 */
- { }, { }, { }, { },
- /* int combiner group 20 */
- { 0, EXT_GIC_ID_MDMA_LCD0 },
- /* int combiner group 21 */
- { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
- /* int combiner group 22 */
- { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
- EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
- /* int combiner group 23 */
- { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
- /* int combiner group 24 */
- { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
- /* int combiner group 25 */
- { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
- /* int combiner group 26 */
- { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
- EXT_GIC_ID_UART4 },
- /* int combiner group 27 */
- { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
- EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
- EXT_GIC_ID_I2C7 },
- /* int combiner group 28 */
- { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
- /* int combiner group 29 */
- { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
- EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
- /* int combiner group 30 */
- { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
- /* int combiner group 31 */
- { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
- /* int combiner group 32 */
- { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
- /* int combiner group 33 */
- { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
- /* int combiner group 34 */
- { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
- /* int combiner group 35 */
- { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
- /* int combiner group 36 */
- { EXT_GIC_ID_MIXER },
- /* int combiner group 37 */
- { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
- EXT_GIC_ID_EXTINT7 },
- /* groups 38-50 */
- { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
- /* int combiner group 51 */
- { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
- /* group 52 */
- { },
- /* int combiner group 53 */
- { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
- /* groups 54-63 */
- { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
-};
-
#define EXYNOS4210_GIC_NIRQ 160
#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
-static void exynos4210_irq_handler(void *opaque, int irq, int level)
-{
- Exynos4210Irq *s = (Exynos4210Irq *)opaque;
-
- /* Bypass */
- qemu_set_irq(s->board_irqs[irq], level);
-}
-
-/*
- * Initialize exynos4210 IRQ subsystem stub.
- */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
-{
- return qemu_allocate_irqs(exynos4210_irq_handler, s,
- EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
-}
-
-/*
- * Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
- */
-void exynos4210_init_board_irqs(Exynos4210Irq *s)
-{
- uint32_t grp, bit, irq_id, n;
-
- for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
- irq_id = 0;
- if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
- n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
- /* MCT_G0 is passed to External GIC */
- irq_id = EXT_GIC_ID_MCT_G0;
- }
- if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
- n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
- /* MCT_G1 is passed to External and GIC */
- irq_id = EXT_GIC_ID_MCT_G1;
- }
- if (irq_id) {
- s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
- s->ext_gic_irq[irq_id-32]);
- } else {
- s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
- s->ext_combiner_irq[n]);
- }
- }
- for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
- /* these IDs are passed to Internal Combiner and External GIC */
- grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
- bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
- irq_id = combiner_grp_to_gic_id[grp -
- EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
-
- if (irq_id) {
- s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
- s->ext_gic_irq[irq_id-32]);
- }
- }
-}
-
-/*
- * Get IRQ number from exynos4210 IRQ subsystem stub.
- * To identify IRQ source use internal combiner group and bit number
- * grp - group number
- * bit - bit number inside group
- */
-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
-{
- return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
-}
-
-/********* GIC part *********/
-
-#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
-
-struct Exynos4210GicState {
- SysBusDevice parent_obj;
-
- MemoryRegion cpu_container;
- MemoryRegion dist_container;
- MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
- MemoryRegion dist_alias[EXYNOS4210_NCPUS];
- uint32_t num_cpu;
- DeviceState *gic;
-};
-
static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
{
Exynos4210GicState *s = (Exynos4210GicState *)opaque;
Object *obj = OBJECT(dev);
Exynos4210GicState *s = EXYNOS4210_GIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
- const char dist_prefix[] = "exynos4210-gic-alias_dist";
- char cpu_alias_name[sizeof(cpu_prefix) + 3];
- char dist_alias_name[sizeof(cpu_prefix) + 3];
SysBusDevice *gicbusdev;
uint32_t n = s->num_cpu;
uint32_t i;
* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
* doesn't figure this out, otherwise and gives spurious warnings.
*/
- assert(n <= EXYNOS4210_NCPUS);
+ assert(n <= EXYNOS4210_GIC_NCPUS);
for (i = 0; i < n; i++) {
+ g_autofree char *cpu_alias_name = g_strdup_printf("exynos4210-gic-alias_cpu%u", i);
+ g_autofree char *dist_alias_name = g_strdup_printf("exynos4210-gic-alias_dist%u", i);
+
/* Map CPU interface per SMP Core */
- sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
memory_region_init_alias(&s->cpu_alias[i], obj,
cpu_alias_name,
sysbus_mmio_get_region(gicbusdev, 1),
EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]);
/* Map Distributor per SMP Core */
- sprintf(dist_alias_name, "%s%x", dist_prefix, i);
memory_region_init_alias(&s->dist_alias[i], obj,
dist_alias_name,
sysbus_mmio_get_region(gicbusdev, 0),
}
type_init(exynos4210_gic_register_types)
-
-/* IRQ OR Gate struct.
- *
- * This device models an OR gate. There are n_in input qdev gpio lines and one
- * output sysbus IRQ line. The output IRQ level is formed as OR between all
- * gpio inputs.
- */
-
-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
-
-struct Exynos4210IRQGateState {
- SysBusDevice parent_obj;
-
- uint32_t n_in; /* inputs amount */
- uint32_t *level; /* input levels */
- qemu_irq out; /* output IRQ */
-};
-
-static Property exynos4210_irq_gate_properties[] = {
- DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static const VMStateDescription vmstate_exynos4210_irq_gate = {
- .name = "exynos4210.irq_gate",
- .version_id = 2,
- .minimum_version_id = 2,
- .fields = (VMStateField[]) {
- VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
- VMSTATE_END_OF_LIST()
- }
-};
-
-/* Process a change in IRQ input. */
-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
-{
- Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
- uint32_t i;
-
- assert(irq < s->n_in);
-
- s->level[irq] = level;
-
- for (i = 0; i < s->n_in; i++) {
- if (s->level[i] >= 1) {
- qemu_irq_raise(s->out);
- return;
- }
- }
-
- qemu_irq_lower(s->out);
-}
-
-static void exynos4210_irq_gate_reset(DeviceState *d)
-{
- Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
-
- memset(s->level, 0, s->n_in * sizeof(*s->level));
-}
-
-/*
- * IRQ Gate initialization.
- */
-static void exynos4210_irq_gate_init(Object *obj)
-{
- Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-
- sysbus_init_irq(sbd, &s->out);
-}
-
-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
-{
- Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
-
- /* Allocate general purpose input signals and connect a handler to each of
- * them */
- qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
-
- s->level = g_malloc0(s->n_in * sizeof(*s->level));
-}
-
-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- dc->reset = exynos4210_irq_gate_reset;
- dc->vmsd = &vmstate_exynos4210_irq_gate;
- device_class_set_props(dc, exynos4210_irq_gate_properties);
- dc->realize = exynos4210_irq_gate_realize;
-}
-
-static const TypeInfo exynos4210_irq_gate_info = {
- .name = TYPE_EXYNOS4210_IRQ_GATE,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(Exynos4210IRQGateState),
- .instance_init = exynos4210_irq_gate_init,
- .class_init = exynos4210_irq_gate_class_init,
-};
-
-static void exynos4210_irq_gate_register_types(void)
-{
- type_register_static(&exynos4210_irq_gate_info);
-}
-
-type_init(exynos4210_irq_gate_register_types)
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
+specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
c->blocked_threads = 0;
}
-static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
+static G_NORETURN
+void block_thread_and_exit(ITCStorageCell *c)
{
c->blocked_threads |= 1ULL << current_cpu->cpu_index;
current_cpu->halted = 1;
--- /dev/null
+/*
+ * QEMU model of the Clock-Reset-LPD (CRL).
+ *
+ * Copyright (c) 2022 Advanced Micro Devices, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/bitops.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+#include "hw/resettable.h"
+
+#include "target/arm/arm-powerctl.h"
+#include "hw/misc/xlnx-versal-crl.h"
+
+#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
+#define XLNX_VERSAL_CRL_ERR_DEBUG 0
+#endif
+
+static void crl_update_irq(XlnxVersalCRL *s)
+{
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+ qemu_set_irq(s->irq, pending);
+}
+
+static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+ crl_update_irq(s);
+}
+
+static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] &= ~val;
+ crl_update_irq(s);
+ return 0;
+}
+
+static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] |= val;
+ crl_update_irq(s);
+ return 0;
+}
+
+static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
+ bool rst_old, bool rst_new)
+{
+ device_cold_reset(dev);
+}
+
+static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
+ bool rst_old, bool rst_new)
+{
+ if (rst_new) {
+ arm_set_cpu_off(armcpu->mp_affinity);
+ } else {
+ arm_set_cpu_on_and_reset(armcpu->mp_affinity);
+ }
+}
+
+#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \
+ bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \
+ bool new_f = FIELD_EX32(new_val, reg, f); \
+ \
+ /* Detect edges. */ \
+ if (dev && old_f != new_f) { \
+ crl_reset_ ## type(s, dev, old_f, new_f); \
+ } \
+}
+
+static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+ REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
+ REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
+ return val64;
+}
+
+static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+ int i;
+
+ /* A single register fans out to all ADMA reset inputs. */
+ for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
+ REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
+ }
+ return val64;
+}
+
+static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+ REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
+ return val64;
+}
+
+static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+ REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
+ return val64;
+}
+
+static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+ REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
+ return val64;
+}
+
+static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+ REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
+ return val64;
+}
+
+static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+ REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
+ return val64;
+}
+
+static const RegisterAccessInfo crl_regs_info[] = {
+ { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
+ .w1c = 0x1,
+ .post_write = crl_status_postw,
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
+ .reset = 0x1,
+ .ro = 0x1,
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
+ .pre_write = crl_enable_prew,
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
+ .pre_write = crl_disable_prew,
+ },{ .name = "WPROT", .addr = A_WPROT,
+ },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN,
+ .reset = 0x1,
+ .rsvd = 0xe,
+ },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL,
+ .reset = 0x24809,
+ .rsvd = 0xf88c00f6,
+ },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG,
+ .reset = 0x2000000,
+ .rsvd = 0x1801210,
+ },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
+ .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
+ R_PLL_STATUS_RPLL_LOCK_MASK,
+ .rsvd = 0xfa,
+ .ro = 0x5,
+ },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL,
+ .reset = 0x2000100,
+ .rsvd = 0xfdfc00ff,
+ },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL,
+ .reset = 0x6000300,
+ .rsvd = 0xf9fc00f8,
+ },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL,
+ .reset = 0x2000800,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL,
+ .reset = 0xe000300,
+ .rsvd = 0xe1fc00f8,
+ },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL,
+ .reset = 0x2000500,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL,
+ .reset = 0xe000a00,
+ .rsvd = 0xf1fc00f8,
+ },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL,
+ .reset = 0xe000a00,
+ .rsvd = 0xf1fc00f8,
+ },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL,
+ .reset = 0x300,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL,
+ .reset = 0x2001900,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL,
+ .reset = 0xc00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL,
+ .reset = 0xc00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL,
+ .reset = 0x600,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL,
+ .reset = 0x600,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL,
+ .reset = 0xc00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL,
+ .reset = 0xc00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL,
+ .reset = 0xc00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL,
+ .reset = 0xc00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL,
+ .reset = 0x300,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL,
+ .reset = 0x2000c00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK,
+ },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL,
+ .reset = 0xf04,
+ .rsvd = 0xfffc00f8,
+ },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
+ .reset = 0x300,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL,
+ .reset = 0x300,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL,
+ .reset = 0x3c00,
+ .rsvd = 0xfdfc00f8,
+ },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5,
+ .reset = 0x17,
+ .rsvd = 0x8,
+ .pre_write = crl_rst_r5_prew,
+ },{ .name = "RST_ADMA", .addr = A_RST_ADMA,
+ .reset = 0x1,
+ .pre_write = crl_rst_adma_prew,
+ },{ .name = "RST_GEM0", .addr = A_RST_GEM0,
+ .reset = 0x1,
+ .pre_write = crl_rst_gem0_prew,
+ },{ .name = "RST_GEM1", .addr = A_RST_GEM1,
+ .reset = 0x1,
+ .pre_write = crl_rst_gem1_prew,
+ },{ .name = "RST_SPARE", .addr = A_RST_SPARE,
+ .reset = 0x1,
+ },{ .name = "RST_USB0", .addr = A_RST_USB0,
+ .reset = 0x1,
+ .pre_write = crl_rst_usb_prew,
+ },{ .name = "RST_UART0", .addr = A_RST_UART0,
+ .reset = 0x1,
+ .pre_write = crl_rst_uart0_prew,
+ },{ .name = "RST_UART1", .addr = A_RST_UART1,
+ .reset = 0x1,
+ .pre_write = crl_rst_uart1_prew,
+ },{ .name = "RST_SPI0", .addr = A_RST_SPI0,
+ .reset = 0x1,
+ },{ .name = "RST_SPI1", .addr = A_RST_SPI1,
+ .reset = 0x1,
+ },{ .name = "RST_CAN0", .addr = A_RST_CAN0,
+ .reset = 0x1,
+ },{ .name = "RST_CAN1", .addr = A_RST_CAN1,
+ .reset = 0x1,
+ },{ .name = "RST_I2C0", .addr = A_RST_I2C0,
+ .reset = 0x1,
+ },{ .name = "RST_I2C1", .addr = A_RST_I2C1,
+ .reset = 0x1,
+ },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD,
+ .reset = 0x33,
+ .rsvd = 0xcc,
+ },{ .name = "RST_GPIO", .addr = A_RST_GPIO,
+ .reset = 0x1,
+ },{ .name = "RST_TTC", .addr = A_RST_TTC,
+ .reset = 0xf,
+ },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP,
+ .reset = 0x1,
+ },{ .name = "RST_SWDT", .addr = A_RST_SWDT,
+ .reset = 0x1,
+ },{ .name = "RST_OCM", .addr = A_RST_OCM,
+ },{ .name = "RST_IPI", .addr = A_RST_IPI,
+ },{ .name = "RST_FPD", .addr = A_RST_FPD,
+ .reset = 0x3,
+ },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE,
+ .reset = 0x1,
+ .rsvd = 0xf8,
+ }
+};
+
+static void crl_reset_enter(Object *obj, ResetType type)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void crl_reset_hold(Object *obj)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+
+ crl_update_irq(s);
+}
+
+static const MemoryRegionOps crl_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void crl_init(Object *obj)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ int i;
+
+ s->reg_array =
+ register_init_block32(DEVICE(obj), crl_regs_info,
+ ARRAY_SIZE(crl_regs_info),
+ s->regs_info, s->regs,
+ &crl_ops,
+ XLNX_VERSAL_CRL_ERR_DEBUG,
+ CRL_R_MAX * 4);
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
+ sysbus_init_irq(sbd, &s->irq);
+
+ for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
+ object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
+ (Object **)&s->cfg.cpu_r5[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
+ object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
+ (Object **)&s->cfg.adma[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
+ object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
+ (Object **)&s->cfg.uart[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
+ object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
+ (Object **)&s->cfg.gem[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+ }
+
+ object_property_add_link(obj, "usb", TYPE_DEVICE,
+ (Object **)&s->cfg.gem[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+}
+
+static void crl_finalize(Object *obj)
+{
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+ register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_crl = {
+ .name = TYPE_XLNX_VERSAL_CRL,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void crl_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_crl;
+
+ rc->phases.enter = crl_reset_enter;
+ rc->phases.hold = crl_reset_hold;
+}
+
+static const TypeInfo crl_info = {
+ .name = TYPE_XLNX_VERSAL_CRL,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalCRL),
+ .class_init = crl_class_init,
+ .instance_init = crl_init,
+ .instance_finalize = crl_finalize,
+};
+
+static void crl_register_types(void)
+{
+ type_register_static(&crl_info);
+}
+
+type_init(crl_register_types)
error_propagate(errp, local_err);
return;
}
+ pci_config_set_interrupt_pin(pci->config, 0);
}
static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
+ pci_config_set_interrupt_pin(conf, 0);
}
static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
msix_notify(dev, pcie_cap_flags_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_cap_flags_get_vector(dev));
- } else {
+ } else if (pci_intx(dev) != -1) {
pci_set_irq(dev, dev->exp.hpev_notified);
}
}
static void hotplug_event_clear(PCIDevice *dev)
{
hotplug_event_update_event_status(dev);
- if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
+ if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 &&
+ !dev->exp.hpev_notified) {
pci_irq_deassert(dev);
}
}
msix_notify(dev, pcie_aer_root_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_aer_root_get_vector(dev));
- } else {
+ } else if (pci_intx(dev) != -1) {
pci_irq_assert(dev);
}
}
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
+
+ qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, true, errp);
}
static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
+
+ qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, false, errp);
}
static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
+
+ qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
return pnv_lpc_isa_create(&chip9->lpc, false, errp);
}
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
+
+ qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
&PNV_PSI(psi8)->xscom_regs);
/* Create LPC controller */
- object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
- &error_abort);
qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
}
/* Create the simplified OCC model */
- object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
+ qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
&PNV_PSI(psi9)->xscom_regs);
/* LPC */
- object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
return;
}
(uint64_t) PNV9_LPCM_BASE(chip));
/* Create the simplified OCC model */
- object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
+ DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
&PNV_PSI(&chip10->psi)->xscom_regs);
/* LPC */
- object_property_set_link(OBJECT(&chip10->lpc), "psi",
- OBJECT(&chip10->psi), &error_abort);
if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
return;
}
(uint64_t) PNV10_LPCM_BASE(chip));
/* Create the simplified OCC model */
- object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
&chip10->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
+ DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(),
static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
{
bool lpc_to_opb_irq = false;
- PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
/* Update LPC controller to OPB line */
if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
/* Reflect the interrupt */
- pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
+ qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
}
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
xdc->dt_xscom = pnv_lpc_dt_xscom;
- plc->psi_irq = PSIHB_IRQ_LPC_I2C;
-
device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
&plc->parent_realize);
}
dc->desc = "PowerNV LPC Controller POWER9";
- plc->psi_irq = PSIHB9_IRQ_LPCHC;
-
device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
&plc->parent_realize);
}
{
PnvLpcController *lpc = PNV_LPC(dev);
- assert(lpc->psi);
-
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
"lpc-hc", LPC_HC_REGS_OPB_SIZE);
memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
&lpc->lpc_hc_regs);
-}
-static Property pnv_lpc_properties[] = {
- DEFINE_PROP_LINK("psi", PnvLpcController, psi, TYPE_PNV_PSI, PnvPsi *),
- DEFINE_PROP_END_OF_LIST(),
-};
+ qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1);
+}
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
{
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
- device_class_set_props(dc, pnv_lpc_properties);
dc->user_creatable = false;
}
}
if (pnv->cpld_irqstate != old_state) {
- pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
+ qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0);
}
}
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
{
bool irq_state;
- PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
val &= 0xffff000000000000ull;
occ->occmisc = val;
irq_state = !!(val >> 63);
- pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
+ qemu_set_irq(occ->psi_irq, irq_state);
}
static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
- poc->psi_irq = PSIHB_IRQ_OCC;
}
static const TypeInfo pnv_occ_power8_type_info = {
dc->desc = "PowerNV OCC Controller (POWER9)";
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
- poc->psi_irq = PSIHB9_IRQ_OCC;
}
static const TypeInfo pnv_occ_power9_type_info = {
PnvOCC *occ = PNV_OCC(dev);
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
- assert(occ->psi);
-
occ->occmisc = 0;
/* XScom region for OCC registers */
memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
occ, "occ-common-area",
PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
-}
-static Property pnv_occ_properties[] = {
- DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
- DEFINE_PROP_END_OF_LIST(),
-};
+ qdev_init_gpio_out(DEVICE(dev), &occ->psi_irq, 1);
+}
static void pnv_occ_class_init(ObjectClass *klass, void *data)
{
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
- device_class_set_props(dc, pnv_occ_properties);
dc->user_creatable = false;
}
/*
* FSP and PSI interrupts are muxed under the same number.
*/
-static const uint32_t xivr_regs[] = {
- [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
+static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
};
-static const uint32_t stat_regs[] = {
- [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
+static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
};
-static const uint64_t stat_bits[] = {
- [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
+static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
[PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
[PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
[PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
};
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
-{
- PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
-}
-
-static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
+static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
{
+ PnvPsi *psi = opaque;
uint32_t xivr_reg;
uint32_t stat_reg;
uint32_t src;
bool masked;
- if (irq > PSIHB_IRQ_EXTERNAL) {
- qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
- return;
- }
-
xivr_reg = xivr_regs[irq];
stat_reg = stat_regs[irq];
ics_set_irq_type(ics, i, true);
}
+ qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs);
+
psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
/* XSCOM region for PSI registers */
ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB_BAR_MASK;
- ppc->irq_set = pnv_psi_power8_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
}
}
};
-static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
+static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
{
+ PnvPsi *psi = opaque;
uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
- if (irq > PSIHB9_NUM_IRQS) {
- qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
- return;
- }
-
if (irq_method & PSIHB9_IRQ_METHOD) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
return;
psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
+ qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs);
+
/* XSCOM region for PSI registers */
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB9_BAR_MASK;
- ppc->irq_set = pnv_psi_power9_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
- g_autofree char *filename;
+ g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
+ machine->firmware);
long bios_size;
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
&error_fatal);
- filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (!filename) {
error_report("Could not find firmware '%s'", machine->firmware);
exit(1);
*
* Copyright 2007 IBM Corporation.
* Authors:
- * Jerone Young <jyoung5@us.ibm.com>
- * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
- * Hollis Blanchard <hollisb@us.ibm.com>
+ * Jerone Young <jyoung5@us.ibm.com>
+ * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
+ * Hollis Blanchard <hollisb@us.ibm.com>
*
* This work is licensed under the GNU GPL license version 2 or later.
*
return H_FUNCTION;
}
-#ifndef CONFIG_TCG
-static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- g_assert_not_reached();
-}
-
-static void hypercall_register_softmmu(void)
-{
- /* hcall-pft */
- spapr_register_hypercall(H_ENTER, h_softmmu);
- spapr_register_hypercall(H_REMOVE, h_softmmu);
- spapr_register_hypercall(H_PROTECT, h_softmmu);
- spapr_register_hypercall(H_READ, h_softmmu);
-
- /* hcall-bulk */
- spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
-}
-#else
-static void hypercall_register_softmmu(void)
-{
- /* DO NOTHING */
-}
-#endif
-
-/* TCG only */
+#ifdef CONFIG_TCG
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
spapr_cpu->nested_host_state = NULL;
}
+static void hypercall_register_nested(void)
+{
+ spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
+ spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
+ spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
+ spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
+}
+
+static void hypercall_register_softmmu(void)
+{
+ /* DO NOTHING */
+}
+#else
+void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+{
+ g_assert_not_reached();
+}
+
+static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ g_assert_not_reached();
+}
+
+static void hypercall_register_nested(void)
+{
+ /* DO NOTHING */
+}
+
+static void hypercall_register_softmmu(void)
+{
+ /* hcall-pft */
+ spapr_register_hypercall(H_ENTER, h_softmmu);
+ spapr_register_hypercall(H_REMOVE, h_softmmu);
+ spapr_register_hypercall(H_PROTECT, h_softmmu);
+ spapr_register_hypercall(H_READ, h_softmmu);
+
+ /* hcall-bulk */
+ spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
+}
+#endif
+
static void hypercall_register_types(void)
{
hypercall_register_softmmu();
spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
- spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
- spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
- spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
- spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
+ hypercall_register_nested();
}
type_init(hypercall_register_types)
if (spapr->fwnmi_machine_check_interlock != cpu->vcpu_id) {
/*
- * The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
+ * The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
* This should be PARAM_ERROR, but Linux calls "ibm,nmi-interlock"
- * for system reset interrupts, despite them not being interlocked.
- * PowerVM silently ignores this and returns success here. Returning
- * failure causes Linux to print the error "FWNMI: nmi-interlock
- * failed: -3", although no other apparent ill effects, this is a
- * regression for the user when enabling FWNMI. So for now, match
- * PowerVM. When most Linux clients are fixed, this could be
- * changed.
- */
+ * for system reset interrupts, despite them not being interlocked.
+ * PowerVM silently ignores this and returns success here. Returning
+ * failure causes Linux to print the error "FWNMI: nmi-interlock
+ * failed: -3", although no other apparent ill effects, this is a
+ * regression for the user when enabling FWNMI. So for now, match
+ * PowerVM. When most Linux clients are fixed, this could be
+ * changed.
+ */
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
return;
}
const struct { int shift; uint32_t mask; } masks[] = {
{ 12, RTAS_DDW_PGSIZE_4K },
{ 16, RTAS_DDW_PGSIZE_64K },
+ { 21, RTAS_DDW_PGSIZE_2M },
{ 24, RTAS_DDW_PGSIZE_16M },
{ 25, RTAS_DDW_PGSIZE_32M },
{ 26, RTAS_DDW_PGSIZE_64M },
uint32_t nodeph, uint32_t pname,
uint32_t valaddr, uint32_t vallen)
{
- char propname[OF_PROPNAME_LEN_MAX + 1];
+ char propname[OF_PROPNAME_LEN_MAX + 1] = "";
uint32_t ret = PROM_ERROR;
int offset, rc;
char trval[64] = "";
#include "qemu/timer.h"
#include "qom/object.h"
+#include "hw/timer/cadence_ttc.h"
+
#ifdef CADENCE_TTC_ERR_DEBUG
#define DB_PRINT(...) do { \
fprintf(stderr, ": %s: ", __func__); \
#define CLOCK_CTRL_PS_EN 0x00000001
#define CLOCK_CTRL_PS_V 0x0000001e
-typedef struct {
- QEMUTimer *timer;
- int freq;
-
- uint32_t reg_clock;
- uint32_t reg_count;
- uint32_t reg_value;
- uint16_t reg_interval;
- uint16_t reg_match[3];
- uint32_t reg_intr;
- uint32_t reg_intr_en;
- uint32_t reg_event_ctrl;
- uint32_t reg_event;
-
- uint64_t cpu_time;
- unsigned int cpu_time_valid;
-
- qemu_irq irq;
-} CadenceTimerState;
-
-#define TYPE_CADENCE_TTC "cadence_ttc"
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
-
-struct CadenceTTCState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- CadenceTimerState timer[3];
-};
-
static void cadence_timer_update(CadenceTimerState *s)
{
qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
#include "qapi/qmp/qdict.h"
+QObject *qdict_crumple(const QDict *src, Error **errp);
+void qdict_flatten(QDict *qdict);
+
void qdict_copy_default(QDict *dst, QDict *src, const char *key);
void qdict_set_default_str(QDict *dst, const char *key, const char *val);
*/
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
-void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
-void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
-void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
-void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
+G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
+G_NORETURN void cpu_loop_exit(CPUState *cpu);
+G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
+G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
/**
* cpu_loop_exit_requested:
* Use the TCGCPUOps hook to record cpu state, do guest operating system
* specific things to raise SIGSEGV, and jump to the main cpu loop.
*/
-void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
- MMUAccessType access_type,
- bool maperr, uintptr_t ra);
+G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
/**
* cpu_loop_exit_sigbus:
* Use the TCGCPUOps hook to record cpu state, do guest operating system
* specific things to raise SIGBUS, and jump to the main cpu loop.
*/
-void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
- MMUAccessType access_type,
- uintptr_t ra);
+G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
+ MMUAccessType access_type,
+ uintptr_t ra);
#else
static inline void mmap_lock(void) {}
#define dh_ctype_ptr void *
#define dh_ctype_cptr const void *
#define dh_ctype_void void
-#define dh_ctype_noreturn void QEMU_NORETURN
+#define dh_ctype_noreturn G_NORETURN void
#define dh_ctype(t) dh_ctype_##t
#ifdef NEED_CPU_H
#include "fpu/softfloat-types.h"
#include "fpu/softfloat-helpers.h"
+#include "qemu/int128.h"
/*----------------------------------------------------------------------------
| Routine to raise any or all of the software IEC/IEEE floating-point
float128 int32_to_float128(int32_t, float_status *status);
float128 int64_to_float128(int64_t, float_status *status);
+float128 int128_to_float128(Int128, float_status *status);
float128 uint64_to_float128(uint64_t, float_status *status);
+float128 uint128_to_float128(Int128, float_status *status);
/*----------------------------------------------------------------------------
| Software half-precision conversion routines.
int32_t float128_to_int32(float128, float_status *status);
int32_t float128_to_int32_round_to_zero(float128, float_status *status);
int64_t float128_to_int64(float128, float_status *status);
+Int128 float128_to_int128(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
+Int128 float128_to_int128_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
+Int128 float128_to_uint128(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
+Int128 float128_to_uint128_round_to_zero(float128, float_status *status);
uint32_t float128_to_uint32(float128, float_status *status);
uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
#define g_test_thorough() qemu_g_test_slow()
#define g_test_quick() (!qemu_g_test_slow())
-#if GLIB_CHECK_VERSION(2,62,0)
-static inline gchar *
-g_date_time_format_iso8601_compat(GDateTime *datetime)
-{
- return g_date_time_format_iso8601(datetime);
-}
+#pragma GCC diagnostic pop
-#define g_date_time_format_iso8601 g_date_time_format_iso8601_compat
+#ifndef G_NORETURN
+#define G_NORETURN G_GNUC_NORETURN
#endif
-#pragma GCC diagnostic pop
-
#endif
#include "hw/or-irq.h"
#include "hw/sysbus.h"
+#include "hw/cpu/a9mpcore.h"
+#include "hw/intc/exynos4210_gic.h"
+#include "hw/intc/exynos4210_combiner.h"
+#include "hw/core/split-irq.h"
#include "target/arm/cpu-qom.h"
#include "qom/object.h"
#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
(EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
- ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
-
-/* IRQs number for external and internal GIC */
-#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
-#define EXYNOS4210_INT_GIC_NIRQ 64
-
#define EXYNOS4210_I2C_NUMBER 9
#define EXYNOS4210_NUM_DMA 3
-typedef struct Exynos4210Irq {
- qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
- qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
- qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
- qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
- qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
-} Exynos4210Irq;
+/*
+ * We need one splitter for every external combiner input, plus
+ * one for every non-zero entry in combiner_grp_to_gic_id[],
+ * minus one for every external combiner ID in second or later
+ * places in a combinermap[] line.
+ * We'll assert in exynos4210_init_board_irqs() if this is wrong.
+ */
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
struct Exynos4210State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
ARMCPU *cpu[EXYNOS4210_NCPUS];
- Exynos4210Irq irqs;
- qemu_irq *irq_table;
+ qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
MemoryRegion chipid_mem;
MemoryRegion iram_mem;
MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
+ qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+ A9MPPrivState a9mpcore;
+ Exynos4210GicState ext_gic;
+ Exynos4210CombinerState int_combiner;
+ Exynos4210CombinerState ext_combiner;
+ SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
};
#define TYPE_EXYNOS4210_SOC "exynos4210"
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info);
-/* Initialize exynos4210 IRQ subsystem stub */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
-
-/* Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210Irq *s);
-
/* Get IRQ number from exynos4210 IRQ subsystem stub.
* To identify IRQ source use internal combiner group and bit number
* grp - group number
* bit - bit number inside group */
uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
- int ext);
-
/*
* exynos4210 UART
*/
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
+#include "hw/cpu/cluster.h"
#include "hw/or-irq.h"
#include "hw/sd/sdhci.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/nvram/xlnx-versal-efuse.h"
#include "hw/ssi/xlnx-versal-ospi.h"
#include "hw/dma/xlnx_csu_dma.h"
+#include "hw/misc/xlnx-versal-crl.h"
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
#define XLNX_VERSAL_NR_ACPUS 2
+#define XLNX_VERSAL_NR_RCPUS 2
#define XLNX_VERSAL_NR_UARTS 2
#define XLNX_VERSAL_NR_GEMS 2
#define XLNX_VERSAL_NR_ADMAS 8
struct {
struct {
MemoryRegion mr;
+ CPUClusterState cluster;
ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
GICv3State gic;
} apu;
VersalUsb2 usb;
} iou;
+ /* Real-time Processing Unit. */
+ struct {
+ MemoryRegion mr;
+ MemoryRegion mr_ps_alias;
+
+ CPUClusterState cluster;
+ ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
+ } rpu;
+
struct {
qemu_or_irq irq_orgate;
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
} xram;
+
+ XlnxVersalCRL crl;
} lpd;
/* The Platform Management Controller subsystem. */
#define VERSAL_TIMER_NS_EL1_IRQ 14
#define VERSAL_TIMER_NS_EL2_IRQ 10
+#define VERSAL_CRL_IRQ 10
#define VERSAL_UART0_IRQ_0 18
#define VERSAL_UART1_IRQ_0 19
#define VERSAL_USB0_IRQ_0 22
#include "hw/or-irq.h"
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
#include "hw/misc/xlnx-zynqmp-crf.h"
+#include "hw/timer/cadence_ttc.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
+#define XLNX_ZYNQMP_NUM_TTC 4
+
/*
* Unimplemented mmio regions needed to boot some images.
*/
qemu_or_irq qspi_irq_orgate;
XlnxZynqMPAPUCtrl apu_ctrl;
XlnxZynqMPCRF crf;
+ CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
*/
AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
-void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
+G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
G_GNUC_PRINTF(2, 3);
/* $(top_srcdir)/cpu.c */
* @do_unaligned_access: Callback for unaligned access handling
* The callback must exit via raising an exception.
*/
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr) QEMU_NORETURN;
+ G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
/**
* @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
#error Cannot include hw/hw.h from user emulation
#endif
-void QEMU_NORETURN hw_error(const char *fmt, ...) G_GNUC_PRINTF(1, 2);
+G_NORETURN void hw_error(const char *fmt, ...) G_GNUC_PRINTF(1, 2);
#endif
--- /dev/null
+/*
+ * Samsung exynos4210 Interrupt Combiner
+ *
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_INTC_EXYNOS4210_COMBINER
+#define HW_INTC_EXYNOS4210_COMBINER
+
+#include "hw/sysbus.h"
+
+/*
+ * State for each output signal of internal combiner
+ */
+typedef struct CombinerGroupState {
+ uint8_t src_mask; /* 1 - source enabled, 0 - disabled */
+ uint8_t src_pending; /* Pending source interrupts before masking */
+} CombinerGroupState;
+
+#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
+
+/* Number of groups and total number of interrupts for the internal combiner */
+#define IIC_NGRP 64
+#define IIC_NIRQ (IIC_NGRP * 8)
+#define IIC_REGSET_SIZE 0x41
+
+struct Exynos4210CombinerState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ struct CombinerGroupState group[IIC_NGRP];
+ uint32_t reg_set[IIC_REGSET_SIZE];
+ uint32_t icipsr[2];
+ uint32_t external; /* 1 means that this combiner is external */
+
+ qemu_irq output_irq[IIC_NGRP];
+};
+
+#endif
--- /dev/null
+/*
+ * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
+ *
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_INTC_EXYNOS4210_GIC_H
+#define HW_INTC_EXYNOS4210_GIC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+
+#define EXYNOS4210_GIC_NCPUS 2
+
+struct Exynos4210GicState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion cpu_container;
+ MemoryRegion dist_container;
+ MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
+ MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
+ uint32_t num_cpu;
+ DeviceState *gic;
+};
+
+#endif
/* Returns a new IRQ with opposite polarity. */
qemu_irq qemu_irq_invert(qemu_irq irq);
-/* Returns a new IRQ which feeds into both the passed IRQs.
- * It's probably better to use the TYPE_SPLIT_IRQ device instead.
- */
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-
/* For internal use in qtest. Similar to qemu_irq_split, but operating
on an existing vector of qemu_irq. */
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
#include "exec/memory.h"
#include "hw/sysbus.h"
+/*
+ * NPCM7XX PWRON STRAP bit fields
+ * 12: SPI0 powered by VSBV3 at 1.8V
+ * 11: System flash attached to BMC
+ * 10: BSP alternative pins.
+ * 9:8: Flash UART command route enabled.
+ * 7: Security enabled.
+ * 6: HI-Z state control.
+ * 5: ECC disabled.
+ * 4: Reserved
+ * 3: JTAG2 enabled.
+ * 2:0: CPU and DRAM clock frequency.
+ */
+#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12)
+#define NPCM7XX_PWRON_STRAP_SFAB BIT(11)
+#define NPCM7XX_PWRON_STRAP_BSPA BIT(10)
+#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8)
+#define FUP_NORM_UART2 3
+#define FUP_PROG_UART3 2
+#define FUP_PROG_UART2 1
+#define FUP_NORM_UART3 0
+#define NPCM7XX_PWRON_STRAP_SECEN BIT(7)
+#define NPCM7XX_PWRON_STRAP_HIZ BIT(6)
+#define NPCM7XX_PWRON_STRAP_ECC BIT(5)
+#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4)
+#define NPCM7XX_PWRON_STRAP_J2EN BIT(3)
+#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x)
+#define CKFRQ_SKIPINIT 0x000
+#define CKFRQ_DEFAULT 0x111
+
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
--- /dev/null
+/*
+ * QEMU model of the Clock-Reset-LPD (CRL).
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+#ifndef HW_MISC_XLNX_VERSAL_CRL_H
+#define HW_MISC_XLNX_VERSAL_CRL_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "target/arm/cpu.h"
+
+#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
+
+REG32(ERR_CTRL, 0x0)
+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x4)
+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_MASK, 0x8)
+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_ENABLE, 0xc)
+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_DISABLE, 0x10)
+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(WPROT, 0x1c)
+ FIELD(WPROT, ACTIVE, 0, 1)
+REG32(PLL_CLK_OTHER_DMN, 0x20)
+ FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
+REG32(RPLL_CTRL, 0x40)
+ FIELD(RPLL_CTRL, POST_SRC, 24, 3)
+ FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
+ FIELD(RPLL_CTRL, FBDIV, 8, 8)
+ FIELD(RPLL_CTRL, BYPASS, 3, 1)
+ FIELD(RPLL_CTRL, RESET, 0, 1)
+REG32(RPLL_CFG, 0x44)
+ FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(RPLL_CFG, LFHF, 10, 2)
+ FIELD(RPLL_CFG, CP, 5, 4)
+ FIELD(RPLL_CFG, RES, 0, 4)
+REG32(RPLL_FRAC_CFG, 0x48)
+ FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
+REG32(PLL_STATUS, 0x50)
+ FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
+ FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
+REG32(RPLL_TO_XPD_CTRL, 0x100)
+ FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
+ FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
+REG32(LPD_TOP_SWITCH_CTRL, 0x104)
+ FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
+ FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
+ FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
+ FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
+REG32(LPD_LSBUS_CTRL, 0x108)
+ FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
+ FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
+ FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
+REG32(CPU_R5_CTRL, 0x10c)
+ FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
+ FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
+ FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
+ FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
+ FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
+ FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
+REG32(IOU_SWITCH_CTRL, 0x114)
+ FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
+ FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
+ FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
+REG32(GEM0_REF_CTRL, 0x118)
+ FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
+ FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
+ FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
+ FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
+REG32(GEM1_REF_CTRL, 0x11c)
+ FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
+ FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
+ FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
+ FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
+REG32(GEM_TSU_REF_CTRL, 0x120)
+ FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
+ FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
+REG32(USB0_BUS_REF_CTRL, 0x124)
+ FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
+ FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
+REG32(UART0_REF_CTRL, 0x128)
+ FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
+ FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
+REG32(UART1_REF_CTRL, 0x12c)
+ FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
+ FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
+REG32(SPI0_REF_CTRL, 0x130)
+ FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
+ FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
+REG32(SPI1_REF_CTRL, 0x134)
+ FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
+ FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
+REG32(CAN0_REF_CTRL, 0x138)
+ FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
+ FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
+REG32(CAN1_REF_CTRL, 0x13c)
+ FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
+ FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
+REG32(I2C0_REF_CTRL, 0x140)
+ FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
+ FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
+REG32(I2C1_REF_CTRL, 0x144)
+ FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
+ FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
+REG32(DBG_LPD_CTRL, 0x148)
+ FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
+ FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
+ FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
+REG32(TIMESTAMP_REF_CTRL, 0x14c)
+ FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
+ FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
+REG32(CRL_SAFETY_CHK, 0x150)
+REG32(PSM_REF_CTRL, 0x154)
+ FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TSTMP_CTRL, 0x158)
+ FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
+ FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
+ FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
+REG32(CPM_TOPSW_REF_CTRL, 0x15c)
+ FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
+ FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
+REG32(USB3_DUAL_REF_CTRL, 0x160)
+ FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
+ FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
+ FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
+REG32(RST_CPU_R5, 0x300)
+ FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
+ FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
+ FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
+ FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
+REG32(RST_ADMA, 0x304)
+ FIELD(RST_ADMA, RESET, 0, 1)
+REG32(RST_GEM0, 0x308)
+ FIELD(RST_GEM0, RESET, 0, 1)
+REG32(RST_GEM1, 0x30c)
+ FIELD(RST_GEM1, RESET, 0, 1)
+REG32(RST_SPARE, 0x310)
+ FIELD(RST_SPARE, RESET, 0, 1)
+REG32(RST_USB0, 0x314)
+ FIELD(RST_USB0, RESET, 0, 1)
+REG32(RST_UART0, 0x318)
+ FIELD(RST_UART0, RESET, 0, 1)
+REG32(RST_UART1, 0x31c)
+ FIELD(RST_UART1, RESET, 0, 1)
+REG32(RST_SPI0, 0x320)
+ FIELD(RST_SPI0, RESET, 0, 1)
+REG32(RST_SPI1, 0x324)
+ FIELD(RST_SPI1, RESET, 0, 1)
+REG32(RST_CAN0, 0x328)
+ FIELD(RST_CAN0, RESET, 0, 1)
+REG32(RST_CAN1, 0x32c)
+ FIELD(RST_CAN1, RESET, 0, 1)
+REG32(RST_I2C0, 0x330)
+ FIELD(RST_I2C0, RESET, 0, 1)
+REG32(RST_I2C1, 0x334)
+ FIELD(RST_I2C1, RESET, 0, 1)
+REG32(RST_DBG_LPD, 0x338)
+ FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
+ FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
+ FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
+ FIELD(RST_DBG_LPD, RESET, 0, 1)
+REG32(RST_GPIO, 0x33c)
+ FIELD(RST_GPIO, RESET, 0, 1)
+REG32(RST_TTC, 0x344)
+ FIELD(RST_TTC, TTC3_RESET, 3, 1)
+ FIELD(RST_TTC, TTC2_RESET, 2, 1)
+ FIELD(RST_TTC, TTC1_RESET, 1, 1)
+ FIELD(RST_TTC, TTC0_RESET, 0, 1)
+REG32(RST_TIMESTAMP, 0x348)
+ FIELD(RST_TIMESTAMP, RESET, 0, 1)
+REG32(RST_SWDT, 0x34c)
+ FIELD(RST_SWDT, RESET, 0, 1)
+REG32(RST_OCM, 0x350)
+ FIELD(RST_OCM, RESET, 0, 1)
+REG32(RST_IPI, 0x354)
+ FIELD(RST_IPI, RESET, 0, 1)
+REG32(RST_SYSMON, 0x358)
+ FIELD(RST_SYSMON, SEQ_RST, 1, 1)
+ FIELD(RST_SYSMON, CFG_RST, 0, 1)
+REG32(RST_FPD, 0x360)
+ FIELD(RST_FPD, SRST, 1, 1)
+ FIELD(RST_FPD, POR, 0, 1)
+REG32(PSM_RST_MODE, 0x370)
+ FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
+ FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
+
+#define CRL_R_MAX (R_PSM_RST_MODE + 1)
+
+#define RPU_MAX_CPU 2
+
+struct XlnxVersalCRL {
+ SysBusDevice parent_obj;
+ qemu_irq irq;
+
+ struct {
+ ARMCPU *cpu_r5[RPU_MAX_CPU];
+ DeviceState *adma[8];
+ DeviceState *uart[2];
+ DeviceState *gem[2];
+ DeviceState *usb;
+ } cfg;
+
+ RegisterInfoArray *reg_array;
+ uint32_t regs[CRL_R_MAX];
+ RegisterInfo regs_info[CRL_R_MAX];
+};
+#endif
/*
* QEMU PowerPC PowerNV LPC controller
*
- * Copyright (c) 2016, IBM Corporation.
+ * Copyright (c) 2016-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_LPC "pnv-lpc"
MemoryRegion xscom_regs;
/* PSI to generate interrupts */
- PnvPsi *psi;
+ qemu_irq psi_irq;
};
-
struct PnvLpcClass {
DeviceClass parent_class;
- int psi_irq;
-
DeviceRealize parent_realize;
};
/*
* QEMU PowerPC PowerNV Emulation of a few OCC related registers
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
#ifndef PPC_PNV_OCC_H
#define PPC_PNV_OCC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_OCC "pnv-occ"
/* OCC Misc interrupt */
uint64_t occmisc;
- PnvPsi *psi;
+ qemu_irq psi_irq;
MemoryRegion xscom_regs;
MemoryRegion sram_regs;
};
-
struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
const MemoryRegionOps *xscom_ops;
- int psi_irq;
};
#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
/*
* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
uint64_t bar_mask;
const char *compat;
int compat_size;
-
- void (*irq_set)(PnvPsi *psi, int, bool state);
};
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
- PSIHB_IRQ_PSI, /* internal use only */
PSIHB_IRQ_FSP, /* internal use only */
PSIHB_IRQ_OCC,
PSIHB_IRQ_FSI,
#define PSI_NUM_INTERRUPTS 6
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
-
/* P9 PSI Interrupts */
#define PSIHB9_IRQ_PSI 0
#define PSIHB9_IRQ_OCC 1
ARCH_MAC99_U3,
};
-#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
-#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
-#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
+#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
+#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
+#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
+#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
+#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
#define RTAS_DDW_PGSIZE_128M 0x20
#define RTAS_DDW_PGSIZE_256M 0x40
#define RTAS_DDW_PGSIZE_16G 0x80
+#define RTAS_DDW_PGSIZE_2M 0x100
/* RTAS tokens */
#define RTAS_TOKEN_BASE 0x2000
--- /dev/null
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ * M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_TIMER_CADENCE_TTC_H
+#define HW_TIMER_CADENCE_TTC_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+typedef struct {
+ QEMUTimer *timer;
+ int freq;
+
+ uint32_t reg_clock;
+ uint32_t reg_count;
+ uint32_t reg_value;
+ uint16_t reg_interval;
+ uint16_t reg_match[3];
+ uint32_t reg_intr;
+ uint32_t reg_intr_en;
+ uint32_t reg_event_ctrl;
+ uint32_t reg_event;
+
+ uint64_t cpu_time;
+ unsigned int cpu_time_valid;
+
+ qemu_irq irq;
+} CadenceTimerState;
+
+#define TYPE_CADENCE_TTC "cadence_ttc"
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
+
+struct CadenceTTCState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ CadenceTimerState timer[3];
+};
+
+#endif
void monitor_register_hmp_info_hrt(const char *name,
HumanReadableText *(*handler)(Error **errp));
+int error_vprintf_unless_qmp(const char *fmt, va_list ap) G_GNUC_PRINTF(1, 0);
+int error_printf_unless_qmp(const char *fmt, ...) G_GNUC_PRINTF(1, 2);
+
#endif /* MONITOR_H */
QDict *qdict_clone_shallow(const QDict *src);
-QObject *qdict_crumple(const QDict *src, Error **errp);
-void qdict_flatten(QDict *qdict);
-
#endif /* QDICT_H */
+++ /dev/null
-#ifndef QEMU_COMMON_H
-#define QEMU_COMMON_H
-
-/* Copyright string for -version arguments, About dialogs, etc */
-#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \
- "Fabrice Bellard and the QEMU Project developers"
-
-/* Bug reporting information for --help arguments, About dialogs, etc */
-#define QEMU_HELP_BOTTOM \
- "See <https://qemu.org/contribute/report-a-bug> for how to report bugs.\n" \
- "More information on the QEMU project at <https://qemu.org>."
-
-/* main function, renamed */
-#if defined(CONFIG_COCOA)
-int qemu_main(int argc, char **argv, char **envp);
-#endif
-
-#endif
--- /dev/null
+/*
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef QEMU_MAIN_H
+#define QEMU_MAIN_H
+
+int qemu_main(int argc, char **argv, char **envp);
+
+#endif /* QEMU_MAIN_H */
#define QEMU_EXTERN_C extern
#endif
-#define QEMU_NORETURN __attribute__ ((__noreturn__))
-
#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
# define QEMU_PACKED __attribute__((gcc_struct, packed))
#else
#define __has_attribute(x) 0 /* compatibility with older GCC */
#endif
+#if defined(__SANITIZE_ADDRESS__) || __has_feature(address_sanitizer)
+# define QEMU_SANITIZE_ADDRESS 1
+#endif
+
+#if defined(__SANITIZE_THREAD__) || __has_feature(thread_sanitizer)
+# define QEMU_SANITIZE_THREAD 1
+#endif
+
/*
* GCC doesn't provide __has_attribute() until GCC 5, but we know all the GCC
* versions we support have the "flatten" attribute. Clang may not have the
#define QEMU_ALWAYS_INLINE
#endif
-/**
- * qemu_build_not_reached()
- *
- * The compiler, during optimization, is expected to prove that a call
- * to this function cannot be reached and remove it. If the compiler
- * supports QEMU_ERROR, this will be reported at compile time; otherwise
- * this will be reported at link time due to the missing symbol.
- */
-extern void QEMU_NORETURN QEMU_ERROR("code path is reachable")
- qemu_build_not_reached_always(void);
-#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
-#define qemu_build_not_reached() qemu_build_not_reached_always()
-#else
-#define qemu_build_not_reached() g_assert_not_reached()
-#endif
-
/**
* In most cases, normal "fallthrough" comments are good enough for
* switch-case statements, but sometimes the compiler has problems
const char *qemu_strchrnul(const char *s, int c);
#endif
time_t mktimegm(struct tm *tm);
-int qemu_fdatasync(int fd);
-int qemu_msync(void *addr, size_t length, int fd);
int qemu_parse_fd(const char *param);
int qemu_strtoi(const char *nptr, const char **endptr, int base,
int *result);
int error_vprintf(const char *fmt, va_list ap) G_GNUC_PRINTF(1, 0);
int error_printf(const char *fmt, ...) G_GNUC_PRINTF(1, 2);
-int error_vprintf_unless_qmp(const char *fmt, va_list ap) G_GNUC_PRINTF(1, 0);
-int error_printf_unless_qmp(const char *fmt, ...) G_GNUC_PRINTF(1, 2);
void error_vreport(const char *fmt, va_list ap) G_GNUC_PRINTF(1, 0);
void warn_vreport(const char *fmt, va_list ap) G_GNUC_PRINTF(1, 0);
--- /dev/null
+#ifndef QEMU_COMMON_H
+#define QEMU_COMMON_H
+
+/* Copyright string for -version arguments, About dialogs, etc */
+#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \
+ "Fabrice Bellard and the QEMU Project developers"
+
+/* Bug reporting information for --help arguments, About dialogs, etc */
+#define QEMU_HELP_BOTTOM \
+ "See <https://qemu.org/contribute/report-a-bug> for how to report bugs.\n" \
+ "More information on the QEMU project at <https://qemu.org>."
+
+#endif
return a >> n;
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+ return (__uint128_t)a >> n;
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
return a << n;
}
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+ uint64_t h = a.hi;
+ if (!n) {
+ return a;
+ }
+ h = h >> (n & 63);
+ if (n >= 64) {
+ return int128_make64(h);
+ } else {
+ return int128_make128((a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h);
+ }
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
uint64_t l = a.lo << (n & 63);
}
#define UINT128_MAX int128_make128(~0LL, ~0LL)
+#define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX)
+#define INT128_MIN int128_make128(0, INT64_MIN)
#endif /* INT128_H */
--- /dev/null
+/*
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef KEYVAL_H_
+#define KEYVAL_H_
+
+QDict *keyval_parse_into(QDict *qdict, const char *params, const char *implied_key,
+ bool *p_help, Error **errp);
+QDict *keyval_parse(const char *params, const char *implied_key,
+ bool *help, Error **errp);
+void keyval_merge(QDict *old, const QDict *new, Error **errp);
+
+#endif /* KEYVAL_H_ */
void qemu_opts_free(QemuOptsList *list);
QemuOptsList *qemu_opts_append(QemuOptsList *dst, QemuOptsList *list);
-QDict *keyval_parse_into(QDict *qdict, const char *params, const char *implied_key,
- bool *p_help, Error **errp);
-QDict *keyval_parse(const char *params, const char *implied_key,
- bool *help, Error **errp);
-void keyval_merge(QDict *old, const QDict *new, Error **errp);
-
G_DEFINE_AUTOPTR_CLEANUP_FUNC(QemuOpts, qemu_opts_del)
#endif
#define assert(x) g_assert(x)
#endif
+/**
+ * qemu_build_not_reached()
+ *
+ * The compiler, during optimization, is expected to prove that a call
+ * to this function cannot be reached and remove it. If the compiler
+ * supports QEMU_ERROR, this will be reported at compile time; otherwise
+ * this will be reported at link time due to the missing symbol.
+ */
+extern G_NORETURN
+void QEMU_ERROR("code path is reachable")
+ qemu_build_not_reached_always(void);
+#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
+#define qemu_build_not_reached() qemu_build_not_reached_always()
+#else
+#define qemu_build_not_reached() g_assert_not_reached()
+#endif
+
/*
* According to waitpid man page:
* WCOREDUMP
void fips_set_state(bool requested);
bool fips_get_state(void);
-/* Return a dynamically allocated pathname denoting a file or directory that is
- * appropriate for storing local state.
- *
- * @relative_pathname need not start with a directory separator; one will be
- * added automatically.
+/* Return a dynamically allocated directory path that is appropriate for storing
+ * local state.
*
* The caller is responsible for releasing the value returned with g_free()
* after use.
*/
-char *qemu_get_local_state_pathname(const char *relative_pathname);
+char *qemu_get_local_state_dir(void);
/* Find program directory, and save it for later usage with
* qemu_get_exec_dir().
#endif
}
+int qemu_fdatasync(int fd);
+
/**
- * qemu_get_host_name:
- * @errp: Error object
- *
- * Operating system agnostic way of querying host name.
+ * Sync changes made to the memory mapped file back to the backing
+ * storage. For POSIX compliant systems this will fallback
+ * to regular msync call. Otherwise it will trigger whole file sync
+ * (including the metadata case there is no support to skip that otherwise)
*
- * Returns allocated hostname (caller should free), NULL on failure.
+ * @addr - start of the memory area to be synced
+ * @length - length of the are to be synced
+ * @fd - file descriptor for the file to be synced
+ * (mandatory only for POSIX non-compliant systems)
*/
-char *qemu_get_host_name(Error **errp);
+int qemu_msync(void *addr, size_t length, int fd);
/**
* qemu_get_host_physmem:
void *qemu_thread_join(QemuThread *thread);
void qemu_thread_get_self(QemuThread *thread);
bool qemu_thread_is_self(QemuThread *thread);
-void qemu_thread_exit(void *retval) QEMU_NORETURN;
+G_NORETURN void qemu_thread_exit(void *retval);
void qemu_thread_naming(bool enable);
struct Notifier;
#else
-void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong addr);
-void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong addr);
+G_NORETURN void helper_unaligned_ld(CPUArchState *env, target_ulong addr);
+G_NORETURN void helper_unaligned_st(CPUArchState *env, target_ulong addr);
#endif /* CONFIG_SOFTMMU */
#endif /* TCG_LDST_H */
#define TCG_CALL_NO_WRITE_GLOBALS 0x0002
/* Helper can be safely suppressed if the return value is not used. */
#define TCG_CALL_NO_SIDE_EFFECTS 0x0004
-/* Helper is QEMU_NORETURN. */
+/* Helper is G_NORETURN. */
#define TCG_CALL_NO_RETURN 0x0008
/* convenience version of most used call flags */
*/
#include "qemu/osdep.h"
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qemu/units.h"
#include "qemu/accel.h"
#include "qemu-version.h"
}
/* abort execution with signal */
-static void QEMU_NORETURN dump_core_and_abort(int target_sig)
+static G_NORETURN
+void dump_core_and_abort(int target_sig)
{
CPUState *cpu = thread_cpu;
CPUArchState *env = cpu->env_ptr;
abi_long arg5, abi_long arg6, abi_long arg7,
abi_long arg8);
extern __thread CPUState *thread_cpu;
-void QEMU_NORETURN cpu_loop(CPUArchState *env);
+G_NORETURN void cpu_loop(CPUArchState *env);
const char *target_strerror(int err);
int get_osversion(void);
void init_qemu_uname_release(void);
static const char *pch;
static sigjmp_buf expr_env;
-static void G_GNUC_PRINTF(2, 3) QEMU_NORETURN
-expr_error(Monitor *mon, const char *fmt, ...)
+static G_NORETURN G_GNUC_PRINTF(2, 3)
+void expr_error(Monitor *mon, const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
return -1;
}
+int error_printf_unless_qmp(const char *fmt, ...)
+{
+ va_list ap;
+ int ret;
+
+ va_start(ap, fmt);
+ ret = error_vprintf_unless_qmp(fmt, ap);
+ va_end(ap);
+ return ret;
+}
static MonitorQAPIEventConf monitor_qapi_event_conf[QAPI_EVENT__MAX] = {
/* Limit guest-triggerable events to 1 per second */
#include "qapi/qmp/qnum.h"
#include "qapi/qmp/qstring.h"
#include "qemu/cutils.h"
-#include "qemu/option.h"
+#include "qemu/keyval.h"
typedef struct StackObject {
const char *name; /* Name of @obj in its parent, if any */
#include "qemu/osdep.h"
#include <getopt.h>
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qemu/qemu-progress.h"
#include "qemu-version.h"
#include "qapi/error.h"
printf(" %s", name);
}
-static void QEMU_NORETURN G_GNUC_PRINTF(1, 2) error_exit(const char *fmt, ...)
+static G_NORETURN G_GNUC_PRINTF(1, 2)
+void error_exit(const char *fmt, ...)
{
va_list ap;
exit(EXIT_FAILURE);
}
-static void QEMU_NORETURN missing_argument(const char *option)
+static G_NORETURN
+void missing_argument(const char *option)
{
error_exit("missing argument for option '%s'", option);
}
-static void QEMU_NORETURN unrecognized_option(const char *option)
+static G_NORETURN
+void unrecognized_option(const char *option)
{
error_exit("unrecognized option '%s'", option);
}
/* Please keep in synch with docs/tools/qemu-img.rst */
-static void QEMU_NORETURN help(void)
+static G_NORETURN
+void help(void)
{
const char *help_msg =
QEMU_IMG_VERSION
#include <termios.h>
#endif
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qapi/error.h"
#include "qemu-io.h"
#include "qemu/error-report.h"
#include <libgen.h>
#include <pthread.h>
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "sysemu/block-backend.h"
GuestFileRead *guest_file_read_unsafe(GuestFileHandle *gfh,
int64_t count, Error **errp);
+/**
+ * qga_get_host_name:
+ * @errp: Error object
+ *
+ * Operating system agnostic way of querying host name.
+ * Compared to g_get_host_name(), it doesn't cache the result.
+ *
+ * Returns allocated hostname (caller should free), NULL on failure.
+ */
+char *qga_get_host_name(Error **errp);
+
#endif
return NULL;
}
+
+#ifndef HOST_NAME_MAX
+# ifdef _POSIX_HOST_NAME_MAX
+# define HOST_NAME_MAX _POSIX_HOST_NAME_MAX
+# else
+# define HOST_NAME_MAX 255
+# endif
+#endif
+
+char *qga_get_host_name(Error **errp)
+{
+ long len = -1;
+ g_autofree char *hostname = NULL;
+
+#ifdef _SC_HOST_NAME_MAX
+ len = sysconf(_SC_HOST_NAME_MAX);
+#endif /* _SC_HOST_NAME_MAX */
+
+ if (len < 0) {
+ len = HOST_NAME_MAX;
+ }
+
+ /* Unfortunately, gethostname() below does not guarantee a
+ * NULL terminated string. Therefore, allocate one byte more
+ * to be sure. */
+ hostname = g_new0(char, len + 1);
+
+ if (gethostname(hostname, len) < 0) {
+ error_setg_errno(errp, errno,
+ "cannot get hostname");
+ return NULL;
+ }
+
+ return g_steal_pointer(&hostname);
+}
}
return head;
}
+
+char *qga_get_host_name(Error **errp)
+{
+ wchar_t tmp[MAX_COMPUTERNAME_LENGTH + 1];
+ DWORD size = G_N_ELEMENTS(tmp);
+
+ if (GetComputerNameW(tmp, &size) == 0) {
+ error_setg_win32(errp, GetLastError(), "failed close handle");
+ return NULL;
+ }
+
+ return g_utf16_to_utf8(tmp, size, NULL, NULL, NULL);
+}
#include "qapi/qmp/qerror.h"
#include "qemu/base64.h"
#include "qemu/cutils.h"
-#include "qemu/atomic.h"
#include "commands-common.h"
/* Maximum captured guest-exec out_data/err_data - 16MB */
ges = g_new0(GuestExecStatus, 1);
- bool finished = qatomic_mb_read(&gei->finished);
+ bool finished = gei->finished;
/* need to wait till output channels are closed
* to be sure we captured all output at this point */
if (gei->has_output) {
- finished = finished && qatomic_mb_read(&gei->out.closed);
- finished = finished && qatomic_mb_read(&gei->err.closed);
+ finished &= gei->out.closed && gei->err.closed;
}
ges->exited = finished;
(int32_t)gpid_to_int64(pid), (uint32_t)status);
gei->status = status;
- qatomic_mb_set(&gei->finished, true);
+ gei->finished = true;
g_spawn_close_pid(pid);
}
done:
g_io_channel_shutdown(ch, true, NULL);
g_io_channel_unref(ch);
- qatomic_mb_set(&p->closed, true);
+ p->closed = true;
g_free(p->data);
return false;
close:
g_io_channel_shutdown(ch, true, NULL);
g_io_channel_unref(ch);
- qatomic_mb_set(&p->closed, true);
+ p->closed = true;
return false;
}
GuestHostName *qmp_guest_get_host_name(Error **errp)
{
GuestHostName *result = NULL;
- g_autofree char *hostname = qemu_get_host_name(errp);
+ g_autofree char *hostname = qga_get_host_name(errp);
/*
* We want to avoid using g_get_host_name() because that
#include <syslog.h>
#include <sys/wait.h>
#endif
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qapi/qmp/json-parser.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qjson.h"
static void
init_dfl_pathnames(void)
{
+ g_autofree char *state = qemu_get_local_state_dir();
+
g_assert(dfl_pathnames.state_dir == NULL);
g_assert(dfl_pathnames.pidfile == NULL);
- dfl_pathnames.state_dir = qemu_get_local_state_pathname(
- QGA_STATE_RELATIVE_DIR);
- dfl_pathnames.pidfile = qemu_get_local_state_pathname(
- QGA_STATE_RELATIVE_DIR G_DIR_SEPARATOR_S "qemu-ga.pid");
+ dfl_pathnames.state_dir = g_build_filename(state, QGA_STATE_RELATIVE_DIR, NULL);
+ dfl_pathnames.pidfile = g_build_filename(state, QGA_STATE_RELATIVE_DIR, "qemu-ga.pid", NULL);
}
static void quit_handler(int sig)
#else
if (level & s->log_level) {
#endif
- gint64 t = g_get_real_time();
- fprintf(s->log_file,
- "%" G_GINT64_FORMAT ".%" G_GINT64_FORMAT
- ": %s: %s\n", t / G_USEC_PER_SEC, t % G_USEC_PER_SEC,
- level_str, msg);
+ g_autoptr(GDateTime) now = g_date_time_new_now_utc();
+ g_autofree char *nowstr = g_date_time_format(now, "%s.%f");
+ fprintf(s->log_file, "%s: %s: %s\n", nowstr, level_str, msg);
fflush(s->log_file);
}
}
* host-side chardev. sleep a bit to mitigate this
*/
if (s->virtio) {
- usleep(100 * 1000);
+ g_usleep(G_USEC_PER_SEC / 10);
}
return true;
default:
#include "qemu/qemu-print.h"
#include "qapi/opts-visitor.h"
#include "qemu/config-file.h"
+#include "qemu/keyval.h"
bool user_creatable_complete(UserCreatable *uc, Error **errp)
{
-Subproject commit 820d43c0a7751e75a8830561f35535dfffd522bd
+Subproject commit 24a7eb35966d93455520bc2debdd7954314b638b
}
echo Found $(find . -name "*.d" | wc -l) object files
-echo $(grep_include -F 'include/qemu-common.h') files include qemu-common.h
echo $(grep_include -F 'hw/hw.h') files include hw/hw.h
echo $(grep_include 'target/[a-z0-9]*/cpu\.h') files include cpu.h
echo $(grep_include -F 'qapi-types.h') files include qapi-types.h
echo osdep.h:
analyze ../include/qemu/osdep.h
-echo qemu-common.h:
-analyze -include ../include/qemu/osdep.h ../include/qemu-common.h
-
echo hw/hw.h:
analyze -include ../include/qemu/osdep.h ../include/hw/hw.h
our $Attribute = qr{
const|
volatile|
- QEMU_NORETURN|
+ G_NORETURN|
G_GNUC_WARN_UNUSED_RESULT|
G_GNUC_NULL_TERMINATED|
QEMU_PACKED|
*/
/* From qemu/compiler.h */
-#define QEMU_NORETURN __attribute__ ((__noreturn__))
+#define G_NORETURN __attribute__ ((__noreturn__))
#define G_GNUC_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
#define G_GNUC_NULL_TERMINATED __attribute__((sentinel))
#include <mpath_persist.h>
#endif
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/main-loop.h"
static void compute_default_paths(void)
{
- socket_path = qemu_get_local_state_pathname("run/qemu-pr-helper.sock");
- pidfile = qemu_get_local_state_pathname("run/qemu-pr-helper.pid");
+ g_autofree char *state = qemu_get_local_state_dir();
+
+ socket_path = g_build_filename(state, "run", "qemu-pr-helper.sock", NULL);
+ pidfile = g_build_filename(state, "run", "qemu-pr-helper.pid", NULL);
}
static void usage(const char *name)
*/
#include "qemu/osdep.h"
-#include "qemu-common.h"
+#include "qemu-main.h"
#include "sysemu/sysemu.h"
#ifdef CONFIG_SDL
-#if defined(__APPLE__) || defined(main)
#include <SDL.h>
-static int qemu_main(int argc, char **argv, char **envp);
-int main(int argc, char **argv)
-{
- return qemu_main(argc, argv, NULL);
-}
-#undef main
-#define main qemu_main
#endif
-#endif /* CONFIG_SDL */
-
-#ifdef CONFIG_COCOA
-#undef main
-#define main qemu_main
-#endif /* CONFIG_COCOA */
-int main(int argc, char **argv, char **envp)
+int qemu_main(int argc, char **argv, char **envp)
{
qemu_init(argc, argv, envp);
qemu_main_loop();
return 0;
}
+
+#ifndef CONFIG_COCOA
+int main(int argc, char **argv)
+{
+ return qemu_main(argc, argv, NULL);
+}
+#endif
*/
#include "qemu/osdep.h"
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "exec/cpu-common.h"
#include "qapi/qapi-visit-qom.h"
#include "qapi/qapi-commands-ui.h"
#include "qapi/qmp/qdict.h"
+#include "block/qdict.h"
#include "qapi/qmp/qerror.h"
#include "sysemu/iothread.h"
#include "qemu/guest-random.h"
+#include "qemu/keyval.h"
#include "config-host.h"
#include "qapi/qmp/qstring.h"
#include "qapi/qobject-input-visitor.h"
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "qemu-version.h"
#include "qemu/config-file.h"
#include "qemu/error-report.h"
#include "qemu/osdep.h"
#include "qemu/error-report.h"
+#include "monitor/monitor.h"
int error_vprintf(const char *fmt, va_list ap)
{
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
void alpha_cpu_list(void);
-void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
-void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
+G_NORETURN void dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
+G_NORETURN void arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
/* This should only be called from translate, via gen_excp.
We expect that ENV->PC has already been updated. */
-void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
+G_NORETURN void helper_excp(CPUAlphaState *env, int excp, int error)
{
CPUState *cs = env_cpu(env);
}
/* This may be called from any of the helpers to set up EXCEPTION_INDEX. */
-void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
- int excp, int error)
+G_NORETURN void dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
+ int excp, int error)
{
CPUState *cs = env_cpu(env);
cpu_loop_exit(cs);
}
-void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr,
- int exc, uint64_t mask)
+G_NORETURN void arith_excp(CPUAlphaState *env, uintptr_t retaddr,
+ int exc, uint64_t mask)
{
env->trap_arg0 = exc;
env->trap_arg1 = mask;
* and target exception level. This should be called from helper functions,
* and never returns because we will longjump back up to the CPU main loop.
*/
-void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
- uint32_t syndrome, uint32_t target_el);
+G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp,
+ uint32_t syndrome, uint32_t target_el);
/*
* Similarly, but also use unwinding to restore cpu state.
*/
-void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp,
+G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el,
uintptr_t ra);
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
/* Raise a data fault alignment exception for the specified virtual address */
-void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
/* arm_cpu_do_transaction_failed: handle a memory system error response
* (eg "no device/memory present at address") by raising an external abort
return pauth_original_ptr(ptr, param);
}
-static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el,
- uintptr_t ra)
+static G_NORETURN
+void pauth_trap(CPUARMState *env, int target_el, uintptr_t ra)
{
raise_exception_ra(env, EXCP_UDEF, syn_pactrap(), target_el, ra);
}
return fsr;
}
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, ARMMMUFaultInfo *fi)
+static G_NORETURN
+void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, ARMMMUFaultInfo *fi)
{
CPUARMState *env = &cpu->env;
int target_el;
#define SF_MANTBITS 23
/* Exceptions processing helpers */
-static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env,
- uint32_t exception,
- uintptr_t pc)
+static G_NORETURN
+void do_raise_exception_err(CPUHexagonState *env,
+ uint32_t exception,
+ uintptr_t pc)
{
CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
cpu_loop_exit_restore(cs, pc);
}
-void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp)
+G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp)
{
do_raise_exception_err(env, excp, 0);
}
}
#ifndef CONFIG_USER_ONLY
-static void QEMU_NORETURN
-hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr)
+static G_NORETURN
+void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
void hppa_cpu_alarm_timer(void *);
int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
#endif
-void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
+G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
#endif /* HPPA_CPU_H */
#include "fpu/softfloat.h"
#include "trace.h"
-void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
+G_NORETURN void HELPER(excp)(CPUHPPAState *env, int excp)
{
CPUState *cs = env_cpu(env);
cpu_loop_exit(cs);
}
-void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
+G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
{
CPUState *cs = env_cpu(env);
#include "exec/helper-proto.h"
#include "helper-tcg.h"
-void QEMU_NORETURN helper_single_step(CPUX86State *env)
+G_NORETURN void helper_single_step(CPUX86State *env)
{
#ifndef CONFIG_USER_ONLY
check_hw_breakpoints(env, true);
#include "exec/helper-proto.h"
#include "helper-tcg.h"
-void QEMU_NORETURN helper_raise_interrupt(CPUX86State *env, int intno,
+G_NORETURN void helper_raise_interrupt(CPUX86State *env, int intno,
int next_eip_addend)
{
raise_interrupt(env, intno, 1, 0, next_eip_addend);
}
-void QEMU_NORETURN helper_raise_exception(CPUX86State *env, int exception_index)
+G_NORETURN void helper_raise_exception(CPUX86State *env, int exception_index)
{
raise_exception(env, exception_index);
}
* env->eip value AFTER the interrupt instruction. It is only relevant if
* is_int is TRUE.
*/
-static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
- int is_int, int error_code,
- int next_eip_addend,
- uintptr_t retaddr)
+static G_NORETURN
+void raise_interrupt2(CPUX86State *env, int intno,
+ int is_int, int error_code,
+ int next_eip_addend,
+ uintptr_t retaddr)
{
CPUState *cs = env_cpu(env);
/* shortcuts to generate exceptions */
-void QEMU_NORETURN raise_interrupt(CPUX86State *env, int intno, int is_int,
- int error_code, int next_eip_addend)
+G_NORETURN void raise_interrupt(CPUX86State *env, int intno, int is_int,
+ int error_code, int next_eip_addend)
{
raise_interrupt2(env, intno, is_int, error_code, next_eip_addend, 0);
}
-void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
- int error_code)
+G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index,
+ int error_code)
{
raise_interrupt2(env, exception_index, 0, error_code, 0, 0);
}
-void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
- int error_code, uintptr_t retaddr)
+G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_index,
+ int error_code, uintptr_t retaddr)
{
raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr);
}
-void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index)
+G_NORETURN void raise_exception(CPUX86State *env, int exception_index)
{
raise_interrupt2(env, exception_index, 0, 0, 0, 0);
}
-void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
- uintptr_t retaddr)
+G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
+ uintptr_t retaddr)
{
raise_interrupt2(env, exception_index, 0, 0, 0, retaddr);
}
void tcg_x86_init(void);
/* excp_helper.c */
-void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
-void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
- uintptr_t retaddr);
-void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
- int error_code);
-void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
- int error_code, uintptr_t retaddr);
-void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
- int error_code, int next_eip_addend);
+G_NORETURN void raise_exception(CPUX86State *env, int exception_index);
+G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
+ uintptr_t retaddr);
+G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index,
+ int error_code);
+G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_index,
+ int error_code, uintptr_t retaddr);
+G_NORETURN void raise_interrupt(CPUX86State *nenv, int intno, int is_int,
+ int error_code, int next_eip_addend);
/* cc_helper.c */
extern const uint8_t parity_table[256];
/* misc_helper.c */
void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask);
-void do_pause(CPUX86State *env) QEMU_NORETURN;
+G_NORETURN void do_pause(CPUX86State *env);
/* sysemu/svm_helper.c */
#ifndef CONFIG_USER_ONLY
-void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
- uint64_t exit_info_1, uintptr_t retaddr);
+G_NORETURN void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
+ uint64_t exit_info_1, uintptr_t retaddr);
void do_vmexit(CPUX86State *env);
#endif
env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
}
-void QEMU_NORETURN helper_rdpmc(CPUX86State *env)
+G_NORETURN void helper_rdpmc(CPUX86State *env)
{
if (((env->cr[4] & CR4_PCE_MASK) == 0 ) &&
((env->hflags & HF_CPL_MASK) != 0)) {
raise_exception_err(env, EXCP06_ILLOP, 0);
}
-void QEMU_NORETURN do_pause(CPUX86State *env)
+G_NORETURN void do_pause(CPUX86State *env)
{
CPUState *cs = env_cpu(env);
cpu_loop_exit(cs);
}
-void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
+G_NORETURN void helper_pause(CPUX86State *env, int next_eip_addend)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC());
env->eip += next_eip_addend;
tlb_flush_page(env_cpu(env), addr);
}
-static void QEMU_NORETURN do_hlt(CPUX86State *env)
+static G_NORETURN
+void do_hlt(CPUX86State *env)
{
CPUState *cs = env_cpu(env);
cpu_loop_exit(cs);
}
-void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend)
+G_NORETURN void helper_hlt(CPUX86State *env, int next_eip_addend)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
env->eip += next_eip_addend;
cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC());
}
-void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend)
+G_NORETURN void helper_mwait(CPUX86State *env, int next_eip_addend)
{
CPUState *cs = env_cpu(env);
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
#endif /* !CONFIG_USER_ONLY */
-void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
void mips_tcg_init(void);
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
const char *mips_exception_name(int32_t exception);
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
- int error_code, uintptr_t pc);
+G_NORETURN void do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
+ int error_code, uintptr_t pc);
-static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
- uint32_t exception,
- uintptr_t pc)
+static inline G_NORETURN
+void do_raise_exception(CPUMIPSState *env,
+ uint32_t exception,
+ uintptr_t pc)
{
do_raise_exception_err(env, exception, 0, pc);
}
void dump_mmu(CPUNios2State *env);
void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
void do_nios2_semihosting(CPUNios2State *env);
#include "exec/exec-all.h"
#include "exception.h"
-void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
+G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp)
{
CPUState *cs = CPU(cpu);
#include "cpu.h"
-void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp);
+G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp);
#endif /* TARGET_OPENRISC_EXCEPTION_H */
raise_exception(cpu, excp);
}
-static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc)
+static G_NORETURN
+void do_range(CPUOpenRISCState *env, uintptr_t pc)
{
CPUState *cs = env_cpu(env);
}
#endif
-void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
-void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
- uintptr_t raddr);
-void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
- uint32_t error_code);
-void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
- uint32_t error_code, uintptr_t raddr);
+G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
+G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
+ uintptr_t raddr);
+G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
+ uint32_t error_code);
+G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
+ uint32_t error_code, uintptr_t raddr);
/* PERFM EBB helper*/
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
register_power5p_common_sprs(env);
register_power5p_lpar_sprs(env);
register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
register_power6_common_sprs(env);
register_power6_dbg_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_pmu_user_sprs(env);
register_power8_tm_sprs(env);
register_power8_pspb_sprs(env);
+ register_power8_dpdes_sprs(env);
register_vtb_sprs(env);
register_power8_ic_sprs(env);
register_power8_book4_sprs(env);
VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
+#define VSX_CVT_FP_TO_INT128(op, tp, rnan) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ ppc_vsr_t t; \
+ int flags; \
+ \
+ helper_reset_fpstatus(env); \
+ t.s128 = float128_to_##tp##_round_to_zero(xb->f128, &env->fp_status); \
+ flags = get_float_exception_flags(&env->fp_status); \
+ if (unlikely(flags & float_flag_invalid)) { \
+ t.VsrD(0) = float_invalid_cvt(env, flags, t.VsrD(0), rnan, 0, GETPC());\
+ t.VsrD(1) = -(t.VsrD(0) & 1); \
+ } \
+ \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_INT128(XSCVQPUQZ, uint128, 0)
+VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
+
/*
* Likewise, except that the result is duplicated into both subwords.
* Power ISA v3.1 has Programming Notes for these insns:
VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
+#define VSX_CVT_INT128_TO_FP(op, tp) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)\
+{ \
+ helper_reset_fpstatus(env); \
+ xt->f128 = tp##_to_float128(xb->s128, &env->fp_status); \
+ helper_compute_fprf_float128(env, xt->f128); \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_INT128_TO_FP(XSCVUQQP, uint128);
+VSX_CVT_INT128_TO_FP(XSCVSQQP, int128);
+
/*
* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
* op - instruction mnemonic
DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
+DEF_HELPER_3(XSCVQPUQZ, void, env, vsr, vsr)
+DEF_HELPER_3(XSCVQPSQZ, void, env, vsr, vsr)
+DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
+DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
DEF_HELPER_4(xscvsdqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvspdp, void, env, vsr, vsr)
@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
+&X_tb rt rb
+@X_tb ...... rt:5 ..... rb:5 .......... . &X_tb
+
&X_tb_rc rt rb rc:bool
@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc
## VSX Binary Floating-Point Convert Instructions
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
+XSCVQPUQZ 111111 ..... 00000 ..... 1101000100 - @X_tb
+XSCVQPSQZ 111111 ..... 01000 ..... 1101000100 - @X_tb
+XSCVUQQP 111111 ..... 00011 ..... 1101000100 - @X_tb
+XSCVSQQP 111111 ..... 01011 ..... 1101000100 - @X_tb
XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
XVCVSPBF16 111100 ..... 10001 ..... 111011011 .. @XX2
bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
#endif
#endif /* PPC_INTERNAL_H */
break;
#if defined(TARGET_PPC64)
case KVM_EXIT_PAPR_HCALL:
- trace_kvm_handle_papr_hcall();
+ trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
run->papr_hcall.ret = spapr_hypercall(cpu,
run->papr_hcall.nr,
run->papr_hcall.args);
kvm_handle_dcr_write(void) "handle dcr write"
kvm_handle_dcr_read(void) "handle dcr read"
kvm_handle_halt(void) "handle halt"
-kvm_handle_papr_hcall(void) "handle PAPR hypercall"
+kvm_handle_papr_hcall(uint64_t hcall) "0x%" PRIx64
kvm_handle_epr(void) "handle epr"
kvm_handle_watchdog_expiry(void) "handle watchdog expiry"
kvm_handle_debug_exception(void) "handle debug exception"
return true;
}
+static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr xt, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_avr_ptr(a->rt);
+ xb = gen_avr_ptr(a->rb);
+ gen_helper(cpu_env, xt, xb);
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
+
+TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
+TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
+TRANS(XSCVQPUQZ, do_helper_env_X_tb, gen_helper_XSCVQPUQZ)
+TRANS(XSCVQPSQZ, do_helper_env_X_tb, gen_helper_XSCVQPSQZ)
+
#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
-void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
- uint32_t exception, uintptr_t pc);
+G_NORETURN void riscv_raise_exception(CPURISCVState *env,
+ uint32_t exception, uintptr_t pc);
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#include "exec/helper-proto.h"
/* Exceptions processing helpers */
-void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
- uint32_t exception, uintptr_t pc)
+G_NORETURN void riscv_raise_exception(CPURISCVState *env,
+ uint32_t exception, uintptr_t pc)
{
CPUState *cs = env_cpu(env);
cs->exception_index = exception;
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
-static inline void QEMU_NORETURN raise_exception(CPURXState *env, int index,
- uintptr_t retaddr);
+static inline G_NORETURN
+void raise_exception(CPURXState *env, int index,
+ uintptr_t retaddr);
static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte)
{
}
/* exception */
-static inline void QEMU_NORETURN raise_exception(CPURXState *env, int index,
- uintptr_t retaddr)
+static inline G_NORETURN
+void raise_exception(CPURXState *env, int index,
+ uintptr_t retaddr)
{
CPUState *cs = env_cpu(env);
cpu_loop_exit_restore(cs, retaddr);
}
-void QEMU_NORETURN helper_raise_privilege_violation(CPURXState *env)
+G_NORETURN void helper_raise_privilege_violation(CPURXState *env)
{
raise_exception(env, 20, GETPC());
}
-void QEMU_NORETURN helper_raise_access_fault(CPURXState *env)
+G_NORETURN void helper_raise_access_fault(CPURXState *env)
{
raise_exception(env, 21, GETPC());
}
-void QEMU_NORETURN helper_raise_illegal_instruction(CPURXState *env)
+G_NORETURN void helper_raise_illegal_instruction(CPURXState *env)
{
raise_exception(env, 23, GETPC());
}
-void QEMU_NORETURN helper_wait(CPURXState *env)
+G_NORETURN void helper_wait(CPURXState *env)
{
CPUState *cs = env_cpu(env);
raise_exception(env, EXCP_HLT, 0);
}
-void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
+G_NORETURN void helper_rxint(CPURXState *env, uint32_t vec)
{
raise_exception(env, 0x100 + vec, 0);
}
-void QEMU_NORETURN helper_rxbrk(CPURXState *env)
+G_NORETURN void helper_rxbrk(CPURXState *env)
{
raise_exception(env, 0x100, 0);
}
bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
#endif
#include "hw/boards.h"
#endif
-void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env,
- uint32_t code, uintptr_t ra)
+G_NORETURN void tcg_s390_program_interrupt(CPUS390XState *env,
+ uint32_t code, uintptr_t ra)
{
CPUState *cs = env_cpu(env);
cpu_loop_exit(cs);
}
-void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
- uintptr_t ra)
+G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
+ uintptr_t ra)
{
g_assert(dxc <= 0xff);
#if !defined(CONFIG_USER_ONLY)
tcg_s390_program_interrupt(env, PGM_DATA, ra);
}
-void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
- uintptr_t ra)
+G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
+ uintptr_t ra)
{
g_assert(vxc <= 0xff);
#if !defined(CONFIG_USER_ONLY)
* this is only for the atomic operations, for which we want to raise a
* specification exception.
*/
-static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t retaddr)
+static G_NORETURN
+void do_unaligned_access(CPUState *cs, uintptr_t retaddr)
{
S390CPU *cpu = S390_CPU(cs);
CPUS390XState *env = &cpu->env;
do_unaligned_access(cs, retaddr);
}
-static void QEMU_NORETURN monitor_event(CPUS390XState *env,
- uint64_t monitor_code,
- uint8_t monitor_class, uintptr_t ra)
+static G_NORETURN
+void monitor_event(CPUS390XState *env,
+ uint64_t monitor_code,
+ uint8_t monitor_class, uintptr_t ra)
{
/* Store the Monitor Code and the Monitor Class Number into the lowcore */
stq_phys(env_cpu(env)->as,
#define TCG_S390X_H
void tcg_s390_tod_updated(CPUState *cs, run_on_cpu_data opaque);
-void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env,
- uint32_t code, uintptr_t ra);
-void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
- uintptr_t ra);
-void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
- uintptr_t ra);
+G_NORETURN void tcg_s390_program_interrupt(CPUS390XState *env,
+ uint32_t code, uintptr_t ra);
+G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
+ uintptr_t ra);
+G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
+ uintptr_t ra);
#endif /* TCG_S390X_H */
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
void sh4_translate_init(void);
void sh4_cpu_list(void);
#endif
}
-static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
- uintptr_t retaddr)
+static inline G_NORETURN
+void raise_exception(CPUSH4State *env, int index,
+ uintptr_t retaddr)
{
CPUState *cs = env_cpu(env);
hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx,
- uintptr_t retaddr);
-void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
+G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx,
+ uintptr_t retaddr);
+G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t);
#ifndef NO_CPU_IO_DEFS
/* cpu_init.c */
}
#ifndef CONFIG_USER_ONLY
-void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx,
- uintptr_t retaddr)
+G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx,
+ uintptr_t retaddr)
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
/* Exception helpers */
-static void QEMU_NORETURN
-raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
- uintptr_t pc, uint32_t fcd_pc)
+static G_NORETURN
+void raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
+ uintptr_t pc, uint32_t fcd_pc)
{
CPUState *cs = env_cpu(env);
/* in case we come from a helper-call we need to restore the PC */
unsigned *n_regs, unsigned *n_core_regs);
int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
#define cpu_list xtensa_cpu_list
}
/* Signal overflow, starting over with fewer guest insns. */
-static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s)
+static G_NORETURN
+void tcg_raise_tb_overflow(TCGContext *s)
{
siglongjmp(s->jmp_trans, -2);
}
return -1;
}
-static void QEMU_NORETURN die_host_rounding(enum rounding rounding)
+static G_NORETURN
+void die_host_rounding(enum rounding rounding)
{
fprintf(stderr, "fatal: '%s' rounding not supported on this host\n",
round_names[rounding]);
}
}
-static void QEMU_NORETURN run_test(void)
+static G_NORETURN
+void run_test(void)
{
unsigned int i;
static int locate_fuzz_memory_regions(Object *child, void *opaque)
{
- const char *name;
MemoryRegion *mr;
if (object_dynamic_cast(child, TYPE_MEMORY_REGION)) {
mr = MEMORY_REGION(child);
if ((memory_region_is_ram(mr) ||
memory_region_is_ram_device(mr) ||
memory_region_is_rom(mr)) == false) {
- name = object_get_canonical_path_component(child);
/*
* We don't want duplicate pointers to the same MemoryRegion, so
* try to remove copies of the pointer, before adding it.
static void socket_send(int fd, const char *buf, size_t size)
{
- size_t offset;
-
- offset = 0;
- while (offset < size) {
- ssize_t len;
+ size_t res = qemu_write_full(fd, buf, size);
- len = write(fd, buf + offset, size - offset);
- if (len == -1 && errno == EINTR) {
- continue;
- }
-
- g_assert_cmpint(len, >, 0);
-
- offset += len;
- }
+ assert(res == size);
}
static void qtest_client_socket_send(QTestState *s, const char *buf)
static void qobject_is_equal_dict_test(void)
{
g_autoptr(QDict) dict_cloned = NULL;
- g_autoptr(QDict) dict_crumpled = NULL;
g_autoptr(QDict) dict_0 = qdict_new();
g_autoptr(QDict) dict_1 = qdict_new();
g_autoptr(QDict) dict_different_key = qdict_new();
dict_different_null_key, dict_longer, dict_shorter,
dict_nested);
- dict_crumpled = qobject_to(QDict, qdict_crumple(dict_1, &error_abort));
- check_equal(dict_crumpled, dict_nested);
-
- qdict_flatten(dict_nested);
- check_equal(dict_0, dict_nested);
-
/* Containing an NaN value will make this dict compare unequal to
* itself */
qdict_put(dict_0, "NaN", qnum_from_double(NAN));
#include "qom/object.h"
#include "qemu/module.h"
#include "qemu/option.h"
+#include "qemu/keyval.h"
#include "qemu/config-file.h"
#include "qom/object_interfaces.h"
endif
endif
-if have_ga and targetos == 'linux' and 'CONFIG_TSAN' not in config_host
+if have_ga and targetos == 'linux'
tests += {'test-qga': ['../qtest/libqtest.c']}
test_deps += {'test-qga': qga}
endif
#include "qapi/qmp/qobject.h"
#include "qapi/qmp/qdict.h"
#include "test-qapi-visit.h"
-#include "qemu/option.h"
+#include "qemu/keyval.h"
typedef bool GenericVisitor (Visitor *, const char *, void **, Error **);
#define CAST_VISIT_TYPE(fn) ((GenericVisitor *)(fn))
test_rshift_one(0xFFFE8000U, 0, 0xFFFFFFFFFFFFFFFEULL, 0x8000000000000000ULL);
}
+static void __attribute__((__noinline__)) ATTRIBUTE_NOCLONE
+test_urshift_one(uint32_t x, int n, uint64_t h, uint64_t l)
+{
+ Int128 a = expand(x);
+ Int128 r = int128_urshift(a, n);
+ g_assert_cmpuint(int128_getlo(r), ==, l);
+ g_assert_cmpuint(int128_gethi(r), ==, h);
+}
+
+static void test_urshift(void)
+{
+ test_urshift_one(0x00010000U, 64, 0x0000000000000000ULL,
+ 0x0000000000000001ULL);
+ test_urshift_one(0x80010000U, 64, 0x0000000000000000ULL,
+ 0x8000000000000001ULL);
+ test_urshift_one(0x7FFE0000U, 64, 0x0000000000000000ULL,
+ 0x7FFFFFFFFFFFFFFEULL);
+ test_urshift_one(0xFFFE0000U, 64, 0x0000000000000000ULL,
+ 0xFFFFFFFFFFFFFFFEULL);
+ test_urshift_one(0x00010000U, 60, 0x0000000000000000ULL,
+ 0x0000000000000010ULL);
+ test_urshift_one(0x80010000U, 60, 0x0000000000000008ULL,
+ 0x0000000000000010ULL);
+ test_urshift_one(0x00018000U, 60, 0x0000000000000000ULL,
+ 0x0000000000000018ULL);
+ test_urshift_one(0x80018000U, 60, 0x0000000000000008ULL,
+ 0x0000000000000018ULL);
+ test_urshift_one(0x7FFE0000U, 60, 0x0000000000000007ULL,
+ 0xFFFFFFFFFFFFFFE0ULL);
+ test_urshift_one(0xFFFE0000U, 60, 0x000000000000000FULL,
+ 0xFFFFFFFFFFFFFFE0ULL);
+ test_urshift_one(0x7FFE8000U, 60, 0x0000000000000007ULL,
+ 0xFFFFFFFFFFFFFFE8ULL);
+ test_urshift_one(0xFFFE8000U, 60, 0x000000000000000FULL,
+ 0xFFFFFFFFFFFFFFE8ULL);
+ test_urshift_one(0x00018000U, 0, 0x0000000000000001ULL,
+ 0x8000000000000000ULL);
+ test_urshift_one(0x80018000U, 0, 0x8000000000000001ULL,
+ 0x8000000000000000ULL);
+ test_urshift_one(0x7FFE0000U, 0, 0x7FFFFFFFFFFFFFFEULL,
+ 0x0000000000000000ULL);
+ test_urshift_one(0xFFFE0000U, 0, 0xFFFFFFFFFFFFFFFEULL,
+ 0x0000000000000000ULL);
+ test_urshift_one(0x7FFE8000U, 0, 0x7FFFFFFFFFFFFFFEULL,
+ 0x8000000000000000ULL);
+ test_urshift_one(0xFFFE8000U, 0, 0xFFFFFFFFFFFFFFFEULL,
+ 0x8000000000000000ULL);
+}
+
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
g_test_add_func("/int128/int128_ge", test_ge);
g_test_add_func("/int128/int128_gt", test_gt);
g_test_add_func("/int128/int128_rshift", test_rshift);
+ g_test_add_func("/int128/int128_urshift", test_urshift);
return g_test_run();
}
#include "qapi/qobject-input-visitor.h"
#include "test-qapi-visit.h"
#include "qemu/cutils.h"
-#include "qemu/option.h"
+#include "qemu/keyval.h"
static void test_keyval_parse(void)
{
TestFixture fix;
int ret;
+#ifdef QEMU_SANITIZE_THREAD
+ {
+ g_test_skip("tsan enabled, https://github.com/google/sanitizers/issues/1116");
+ return 0;
+ }
+#endif
+
setlocale (LC_ALL, "");
g_test_init(&argc, &argv, NULL);
fixture_setup(&fix, NULL, NULL);
{
g_autofree gchar *sk_name = NULL;
g_autofree gchar *pidfile = NULL;
+ g_autofree gchar *state = NULL;
g_autofree gchar *dir = NULL;
Error *local_err = NULL;
- dir = qemu_get_local_state_pathname("run/virtiofsd");
+ state = qemu_get_local_state_dir();
+ dir = g_build_filename(state, "run", "virtiofsd", NULL);
if (g_mkdir_with_parents(dir, S_IRWXU) < 0) {
fuse_log(FUSE_LOG_ERR, "%s: Failed to create directory %s: %s\n",
#include "qemu/osdep.h"
#include "qemu/timer.h"
#include "qemu-version.h"
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
#include "fuse_virtio.h"
#include "fuse_log.h"
#include "fuse_lowlevel.h"
#import <Cocoa/Cocoa.h>
#include <crt_externs.h>
-#include "qemu-common.h"
+#include "qemu/help-texts.h"
+#include "qemu-main.h"
#include "ui/clipboard.h"
#include "ui/console.h"
#include "ui/input.h"
#include "qemu/cutils.h"
#include "qemu/help_option.h"
#include "io/dns-resolver.h"
+#include "monitor/monitor.h"
#define VNC_REFRESH_INTERVAL_BASE GUI_REFRESH_INTERVAL_DEFAULT
#define VNC_REFRESH_INTERVAL_INC 50
}
} else {
struct qemu_signalfd_siginfo buffer;
- size_t offset = 0;
-
memset(&buffer, 0, sizeof(buffer));
buffer.ssi_signo = sig;
- while (offset < sizeof(buffer)) {
- ssize_t len;
-
- len = write(info->fd, (char *)&buffer + offset,
- sizeof(buffer) - offset);
- if (len == -1 && errno == EINTR) {
- continue;
- }
-
- if (len <= 0) {
- return NULL;
- }
-
- offset += len;
+ if (qemu_write_full(info->fd, &buffer, sizeof(buffer)) != sizeof(buffer)) {
+ return NULL;
}
}
}
return t;
}
-/*
- * Make sure data goes on disk, but if possible do not bother to
- * write out the inode just for timestamp updates.
- *
- * Unfortunately even in 2009 many operating systems do not support
- * fdatasync and have to fall back to fsync.
- */
-int qemu_fdatasync(int fd)
-{
-#ifdef CONFIG_FDATASYNC
- return fdatasync(fd);
-#else
- return fsync(fd);
-#endif
-}
-
-/**
- * Sync changes made to the memory mapped file back to the backing
- * storage. For POSIX compliant systems this will fallback
- * to regular msync call. Otherwise it will trigger whole file sync
- * (including the metadata case there is no support to skip that otherwise)
- *
- * @addr - start of the memory area to be synced
- * @length - length of the are to be synced
- * @fd - file descriptor for the file to be synced
- * (mandatory only for POSIX non-compliant systems)
- */
-int qemu_msync(void *addr, size_t length, int fd)
-{
-#ifdef CONFIG_POSIX
- size_t align_mask = ~(qemu_real_host_page_size() - 1);
-
- /**
- * There are no strict reqs as per the length of mapping
- * to be synced. Still the length needs to follow the address
- * alignment changes. Additionally - round the size to the multiple
- * of PAGE_SIZE
- */
- length += ((uintptr_t)addr & (qemu_real_host_page_size() - 1));
- length = (length + ~align_mask) & align_mask;
-
- addr = (void *)((uintptr_t)addr & align_mask);
-
- return msync(addr, length, MS_SYNC);
-#else /* CONFIG_POSIX */
- /**
- * Perform the sync based on the file descriptor
- * The sync range will most probably be wider than the one
- * requested - but it will still get the job done
- */
- return qemu_fdatasync(fd);
-#endif /* CONFIG_POSIX */
-}
-
static int64_t suffix_mul(char suffix, int64_t unit)
{
switch (qemu_toupper(suffix)) {
return ret;
}
-int error_printf_unless_qmp(const char *fmt, ...)
-{
- va_list ap;
- int ret;
-
- va_start(ap, fmt);
- ret = error_vprintf_unless_qmp(fmt, ap);
- va_end(ap);
- return ret;
-}
-
static Location std_loc = {
.kind = LOC_NONE
};
static char *
real_time_iso8601(void)
{
-#if GLIB_CHECK_VERSION(2, 62, 0)
+#if GLIB_CHECK_VERSION(2,62,0)
g_autoptr(GDateTime) dt = g_date_time_new_from_unix_utc(g_get_real_time());
+ /* ignore deprecation warning, since GLIB_VERSION_MAX_ALLOWED is 2.56 */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
return g_date_time_format_iso8601(dt);
+#pragma GCC diagnostic pop
#else
GTimeVal tv;
g_get_current_time(&tv);
#include "qapi/qmp/qlist.h"
#include "qapi/qmp/qstring.h"
#include "qemu/cutils.h"
+#include "qemu/keyval.h"
#include "qemu/help_option.h"
-#include "qemu/option.h"
/*
* Convert @key to a list index.
return readv_writev(fd, iov, iov_cnt, true);
}
#endif
+
+/*
+ * Make sure data goes on disk, but if possible do not bother to
+ * write out the inode just for timestamp updates.
+ *
+ * Unfortunately even in 2009 many operating systems do not support
+ * fdatasync and have to fall back to fsync.
+ */
+int qemu_fdatasync(int fd)
+{
+#ifdef CONFIG_FDATASYNC
+ return fdatasync(fd);
+#else
+ return fsync(fd);
+#endif
+}
.l_len = 0,
};
- fd = qemu_open_old(path, O_CREAT | O_WRONLY, S_IRUSR | S_IWUSR);
+ fd = qemu_create(path, O_WRONLY, S_IRUSR | S_IWUSR, errp);
if (fd == -1) {
- error_setg_errno(errp, errno, "Cannot open pid file");
return false;
}
}
snprintf(pidstr, sizeof(pidstr), FMT_pid "\n", getpid());
- if (write(fd, pidstr, strlen(pidstr)) != strlen(pidstr)) {
+ if (qemu_write_full(fd, pidstr, strlen(pidstr)) != strlen(pidstr)) {
error_setg(errp, "Failed to write pid file");
goto fail_unlink;
}
}
char *
-qemu_get_local_state_pathname(const char *relative_pathname)
+qemu_get_local_state_dir(void)
{
- g_autofree char *dir = g_strdup_printf("%s/%s",
- CONFIG_QEMU_LOCALSTATEDIR,
- relative_pathname);
- return get_relocated_path(dir);
+ return get_relocated_path(CONFIG_QEMU_LOCALSTATEDIR);
}
void qemu_set_tty_echo(int fd, bool echo)
action->sa_sigaction(info->ssi_signo, &si, NULL);
}
-#ifndef HOST_NAME_MAX
-# ifdef _POSIX_HOST_NAME_MAX
-# define HOST_NAME_MAX _POSIX_HOST_NAME_MAX
-# else
-# define HOST_NAME_MAX 255
-# endif
-#endif
-
-char *qemu_get_host_name(Error **errp)
-{
- long len = -1;
- g_autofree char *hostname = NULL;
-
-#ifdef _SC_HOST_NAME_MAX
- len = sysconf(_SC_HOST_NAME_MAX);
-#endif /* _SC_HOST_NAME_MAX */
-
- if (len < 0) {
- len = HOST_NAME_MAX;
- }
-
- /* Unfortunately, gethostname() below does not guarantee a
- * NULL terminated string. Therefore, allocate one byte more
- * to be sure. */
- hostname = g_new0(char, len + 1);
-
- if (gethostname(hostname, len) < 0) {
- error_setg_errno(errp, errno,
- "cannot get hostname");
- return NULL;
- }
-
- return g_steal_pointer(&hostname);
-}
-
size_t qemu_get_host_physmem(void)
{
#ifdef _SC_PHYS_PAGES
}
return 0;
}
+
+int qemu_msync(void *addr, size_t length, int fd)
+{
+ size_t align_mask = ~(qemu_real_host_page_size() - 1);
+
+ /**
+ * There are no strict reqs as per the length of mapping
+ * to be synced. Still the length needs to follow the address
+ * alignment changes. Additionally - round the size to the multiple
+ * of PAGE_SIZE
+ */
+ length += ((uintptr_t)addr & (qemu_real_host_page_size() - 1));
+ length = (length + ~align_mask) & align_mask;
+
+ addr = (void *)((uintptr_t)addr & align_mask);
+
+ return msync(addr, length, MS_SYNC);
+}
}
char *
-qemu_get_local_state_pathname(const char *relative_pathname)
+qemu_get_local_state_dir(void)
{
HRESULT result;
char base_path[MAX_PATH+1] = "";
g_critical("CSIDL_COMMON_APPDATA unavailable: %ld", (long)result);
abort();
}
- return g_strdup_printf("%s" G_DIR_SEPARATOR_S "%s", base_path,
- relative_pathname);
+ return g_strdup(base_path);
}
void qemu_set_tty_echo(int fd, bool echo)
return true;
}
-char *qemu_get_host_name(Error **errp)
-{
- wchar_t tmp[MAX_COMPUTERNAME_LENGTH + 1];
- DWORD size = G_N_ELEMENTS(tmp);
-
- if (GetComputerNameW(tmp, &size) == 0) {
- error_setg_win32(errp, GetLastError(), "failed close handle");
- return NULL;
- }
-
- return g_utf16_to_utf8(tmp, size, NULL, NULL, NULL);
-}
-
size_t qemu_get_host_physmem(void)
{
MEMORYSTATUSEX statex;
}
return 0;
}
+
+int qemu_msync(void *addr, size_t length, int fd)
+{
+ /**
+ * Perform the sync based on the file descriptor
+ * The sync range will most probably be wider than the one
+ * requested - but it will still get the job done
+ */
+ return qemu_fdatasync(fd);
+}
projects / mirror_qemu.git / commitdiff