drm/powerplay: label internally used symbols as static

Used sparse(make C=1) to find these loose ends.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e514f02ca0d1d239aaa6840d8bb949c4661f9c77..fe4948aa662fcbc2b2c05d4c2b0accc744a2d262 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1695,7 +1695,7 @@ static int smu_enable_umd_pstate(void *handle,
        return 0;
 }
 
-int smu_adjust_power_state_dynamic(struct smu_context *smu,
+static int smu_adjust_power_state_dynamic(struct smu_context *smu,
                                   enum amd_dpm_forced_level level,
                                   bool skip_display_settings)
 {

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 753cb2cf6b77e668fd4ec93f3eb0e7ce709b0563..2c9cac8c170c18fe38b1a97ee5081e2e9c084129 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1487,7 +1487,7 @@ static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
        int tmp_result, result = 0;
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index a6c6a793e98eef8d413c434ccfdd099c2d6b41a5..35ed47ebaf09d4d44840f5043f751af14b30af7a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1879,7 +1879,7 @@ static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
        return 0;
 }
 
-int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
+static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 {
        struct smu8_hwmgr *data = hwmgr->backend;
        struct phm_uvd_clock_voltage_dependency_table *ptable =

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 675c7cab7cfc5992121aaab273e02e9df567a07a..c378a000c934440dc247d8d680fe89c778e16e7c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -90,7 +90,7 @@ typedef enum {
 
 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
 
-struct vega10_power_state *cast_phw_vega10_power_state(
+static struct vega10_power_state *cast_phw_vega10_power_state(
                                  struct pp_hw_power_state *hw_ps)
 {
        PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
@@ -100,7 +100,7 @@ struct vega10_power_state *cast_phw_vega10_power_state(
        return (struct vega10_power_state *)hw_ps;
 }
 
-const struct vega10_power_state *cast_const_phw_vega10_power_state(
+static const struct vega10_power_state *cast_const_phw_vega10_power_state(
                                 const struct pp_hw_power_state *hw_ps)
 {
        PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
@@ -2330,7 +2330,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
 {
        struct vega10_hwmgr *data = hwmgr->backend;
 
-       if (data->smu_features[GNLD_ACG].supported && 
+       if (data->smu_features[GNLD_ACG].supported &&
            data->smu_features[GNLD_ACG].enabled)
                if (!vega10_enable_smc_features(hwmgr, false,
                        data->smu_features[GNLD_ACG].smu_feature_bitmap))
@@ -3905,7 +3905,7 @@ static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
                        NULL);
 }
 
-int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
                struct pp_display_clock_request *clock_req)
 {
        int result = 0;
@@ -4672,7 +4672,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
        return result;
 }
 
-int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
+static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
 {
        struct vega10_hwmgr *data = hwmgr->backend;
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index 7783c7fd7ccb0a58e906d0440f25eab9e2612315..468bdd6f669733afaf2b5465256b134f64c13f99 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -499,7 +499,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 {
        int ret;
        struct vega10_hwmgr *data = hwmgr->backend;
@@ -602,7 +602,7 @@ int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
+static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 {
 /* If the fantable setup has failed we could have disabled
  * PHM_PlatformCaps_MicrocodeFanControl even after

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index f4d1692cccf3a388b013b463f676941b1ee42902..a678a67f1c0d0429a3c0bd1da3385d747eb74139 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1436,7 +1436,7 @@ static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
                struct pp_display_clock_request *clock_req)
 {
        int result = 0;
@@ -2404,7 +2404,7 @@ static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
        return result;
 }
 
-int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
+static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
 {
        struct vega12_hwmgr *data =
                        (struct vega12_hwmgr *)(hwmgr->backend);

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
index 9817f7a5ed29603f90fd18a02b8e8e982f182cfa..195d8539fbb431c8837e660cbe2522d11311da1f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
@@ -263,7 +263,7 @@ static int init_powerplay_table_information(
        return result;
 }
 
-int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
+static int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
 {
        int result = 0;
        const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
index c85806a6f62e3f6dcb185a9e6e6d38bbd9bf646e..c15b9756025d9c523bb789195b98784bc3c5b51d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
@@ -251,7 +251,7 @@ int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+static int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 {
        int ret;
        struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
@@ -274,7 +274,7 @@ int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
+static int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 {
        /* If the fantable setup has failed we could have disabled
         * PHM_PlatformCaps_MicrocodeFanControl even after

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 9ff470f1b826cd570339eba862827b6c413bc659..3b8839641770bef71f9e2f39db60acba86845ecb 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1981,7 +1981,7 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_
        return ret;
 }
 
-int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
+static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
 {
        struct vega20_hwmgr *data =
                        (struct vega20_hwmgr *)(hwmgr->backend);
@@ -2253,7 +2253,7 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
        return ret;
 }
 
-int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
                struct pp_display_clock_request *clock_req)
 {
        int result = 0;
@@ -3589,7 +3589,7 @@ static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
        return result;
 }
 
-int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
+static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
 {
        struct vega20_hwmgr *data =
                        (struct vega20_hwmgr *)(hwmgr->backend);

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 769e031d489ad670cab8251d6019bf30705937d2..0957957a2cf568be6766eb01acb850b32c8c52c0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1805,7 +1805,7 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
        return 0;
 }
 
-int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
+static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
                                enum smu_clk_type clk_type,
                                uint32_t *min, uint32_t *max)
 {
@@ -1821,7 +1821,7 @@ int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
        return ret;
 }
 
-int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
+static int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
                                      enum smu_clk_type clk_type,
                                      uint32_t min, uint32_t max)
 {

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 56923a96b4502fa26d47017c61d3600c8fb84543..02159ca29fa29202ce38c83d9b6bb3c9ad3f3f21 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -183,7 +183,7 @@ static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
+static bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
 {
        return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
                        CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 398e7e3587de141d455ba95dafc2879754580754..4bfadb49521bcedbaea683df4c6325c1d4bca795 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -1083,7 +1083,7 @@ static int tonga_populate_single_memory_level(
        return result;
 }
 
-int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 {
        struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
        struct tonga_smumgr *smu_data =