drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

WA to enable HW L1 Banking fix that allows aniso to operate
at full sample rate.

References: HSD#1937670

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230723.20898-1-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae340047064fc406c3a70d3e8dfb527348d..1ad22a824921a94cfe4957ce0c869cc9a79c68e9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8072,6 +8072,7 @@ enum {
 #define   HSW_SAMPLE_C_PERFORMANCE     (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC  (1<<5)
+#define   CNL_FAST_ANISO_L1_BANKING_FIX        (1<<4)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS        (1<<1)
 
 #define GEN9_HALF_SLICE_CHICKEN7       _MMIO(0xe194)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a6ac9d0a415697149fc9677239fcb059d59e7d45..4b9b7828802d369f50641b24c25de5c38f7ba5cc 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
        /* WaPushConstantDereferenceHoldDisable:cnl */
        WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 
+       /* FtrEnableFastAnisoL1BankingFix: cnl */
+       WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
+
        /* WaEnablePreemptionGranularityControlByUMD:cnl */
        ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
        if (ret)