Fix BD flag handling, cause register contents, implement some more bits

for R2 interrupt handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/hw/mips_int.c b/hw/mips_int.c
index 93d599fc6022602cbb34f5e2f044eccf02ce0d73..7f9f15305b4e13c662472a0b9847cfd47eeb17e6 100644 (file)
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -20,20 +20,15 @@ void cpu_mips_update_irq(CPUState *env)
 
 void cpu_mips_irq_request(void *opaque, int irq, int level)
 {
-    CPUState *env = first_cpu;
-   
-    uint32_t mask;
+    CPUState *env = (CPUState *)opaque;
 
-    if (irq >= 16)
+    if (irq < 0 || irq > 7)
         return;
 
-    mask = 1 << (irq + CP0Ca_IP);
-
     if (level) {
-        env->CP0_Cause |= mask;
+        env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
     } else {
-        env->CP0_Cause &= ~mask;
+        env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
     }
     cpu_mips_update_irq(env);
 }
-

diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index bc83036b34abef511be224ebcc06be2cffc8047f..055ee5b892517924cf39bae963108e8d5aaa12cf 100644 (file)
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -28,6 +28,9 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count,
     uint64_t now, next;
     uint32_t tmp;
 
+    if (env->CP0_Cause & (1 << CP0Ca_DC))
+        return;
+
     tmp = count;
     if (count == compare)
         tmp++;
@@ -57,6 +60,8 @@ void cpu_mips_store_count (CPUState *env, uint32_t value)
 void cpu_mips_store_compare (CPUState *env, uint32_t value)
 {
     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        env->CP0_Cause &= ~(1 << CP0Ca_TI);
     cpu_mips_irq_request(env, 7, 0);
 }
 
@@ -71,6 +76,8 @@ static void mips_timer_cb (void *opaque)
     }
 #endif
     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        env->CP0_Cause |= 1 << CP0Ca_TI;
     cpu_mips_irq_request(env, 7, 1);
 }
 

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 9ba401785beafba526a8a462efa0c538bbe5cd7d..0b23f359f035a4fde1e626554ead15d029e6d48d 100644 (file)
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -295,9 +295,12 @@ void do_interrupt (CPUState *env)
             /* If the exception was raised from a delay slot,
                come back to the jump.  */
             env->CP0_DEPC = env->PC - 4;
+            if (!(env->hflags & MIPS_HFLAG_EXL))
+                env->CP0_Cause |= (1 << CP0Ca_BD);
             env->hflags &= ~MIPS_HFLAG_BMASK;
         } else {
             env->CP0_DEPC = env->PC;
+            env->CP0_Cause &= ~(1 << CP0Ca_BD);
         }
     enter_debug_mode:
         env->hflags |= MIPS_HFLAG_DM;
@@ -318,9 +321,12 @@ void do_interrupt (CPUState *env)
             /* If the exception was raised from a delay slot,
                come back to the jump.  */
             env->CP0_ErrorEPC = env->PC - 4;
+            if (!(env->hflags & MIPS_HFLAG_EXL))
+                env->CP0_Cause |= (1 << CP0Ca_BD);
             env->hflags &= ~MIPS_HFLAG_BMASK;
         } else {
             env->CP0_ErrorEPC = env->PC;
+            env->CP0_Cause &= ~(1 << CP0Ca_BD);
         }
         env->hflags |= MIPS_HFLAG_ERL;
        env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
@@ -364,7 +370,8 @@ void do_interrupt (CPUState *env)
         goto set_EPC;
     case EXCP_CpU:
         cause = 11;
-        env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
+        env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
+                         (env->error_code << CP0Ca_CE);
         goto set_EPC;
     case EXCP_OVERFLOW:
         cause = 12;
@@ -385,11 +392,12 @@ void do_interrupt (CPUState *env)
             /* If the exception was raised from a delay slot,
                come back to the jump.  */
             env->CP0_EPC = env->PC - 4;
-            env->CP0_Cause |= 0x80000000;
+            if (!(env->hflags & MIPS_HFLAG_EXL))
+                env->CP0_Cause |= (1 << CP0Ca_BD);
             env->hflags &= ~MIPS_HFLAG_BMASK;
         } else {
             env->CP0_EPC = env->PC;
-            env->CP0_Cause &= ~0x80000000;
+            env->CP0_Cause &= ~(1 << CP0Ca_BD);
         }
         if (env->CP0_Status & (1 << CP0St_BEV)) {
             env->PC = (int32_t)0xBFC00200;

diff --git a/target-mips/op.c b/target-mips/op.c
index 7c7ce3ba3e45a9475494890bdff8456848c7d014..a286cefe5d0bd097b3889bee37073c9d19f4b3ee 100644 (file)
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1397,7 +1397,12 @@ void op_mtc0_srsmap (void)
 
 void op_mtc0_cause (void)
 {
-    env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
+    uint32_t mask = 0x00C00300;
+
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        mask |= 1 << CP0Ca_DC;
+
+    env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
 
     /* Handle the software interrupt as an hardware one, as they
        are very similar */