drm/tegra: dc: Make sure to set the module clock rate

When applying the PLL changes from the computed state object, make sure
to set the rate of the display controller module clock. Failing to do so
can yield to a situation where the parent will be set to the proper
pixel clock, but the module clock will be divided down to the rate that
is happened to be set to before the parent rate change.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 6a43dff70822a4a9a6932e4c71af971d8f8c9626..d5a63230e50967904919c3d6f594a12a8d412734 100644 (file)
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1138,6 +1138,11 @@ static void tegra_dc_commit_state(struct tegra_dc *dc,
 
        value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
        tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
+
+       err = clk_set_rate(dc->clk, state->pclk);
+       if (err < 0)
+               dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
+                       dc->clk, state->pclk, err);
 }
 
 static void tegra_dc_stop(struct tegra_dc *dc)