drm/i915: Increase max fence pitch limit to 256KB on IVB+

BSpec contains several scattered notes which state that the maximum
fence stride was increased to 256KB on IVB.

Testing on real hardware agrees.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index b56185f4babb613410285ffe7ba85ecb21c52330..537545be69db89fb8c2d19e692a94cca0b418bf8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
                tile_width = 512;
 
        /* check maximum stride & object size */
-       if (INTEL_INFO(dev)->gen >= 4) {
-               /* i965 stores the end address of the gtt mapping in the fence
-                * reg, so dont bother to check the size */
+       /* i965+ stores the end address of the gtt mapping in the fence
+        * reg, so dont bother to check the size */
+       if (INTEL_INFO(dev)->gen >= 7) {
+               if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
+                       return false;
+       } else if (INTEL_INFO(dev)->gen >= 4) {
                if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
                        return false;
        } else {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b9ec9bcd383dd7950eda614556cbd16f4d934e6..e0fc0706e0344bafddd87207862d319b0e793d55 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -430,6 +430,7 @@
 
 #define FENCE_REG_SANDYBRIDGE_0                0x100000
 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT        32
+#define   GEN7_FENCE_MAX_PITCH_VAL     0x0800
 
 /* control register for cpu gtt access */
 #define TILECTL                                0x101000