target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry

We already print various lines of information when we take an
exception, including the ELR and (if relevant) the FAR. Now
that FEAT_NV means that we might report something other than
the old PSTATE to the guest as the SPSR, it's worth logging
this as well.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4550ff7ffde016cf4eb9224b16f16edbcd35fd99..dc8f14f43316085ca427f02724b6a07fa1cab67e 100644 (file)
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11416,6 +11416,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     }
     env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
 
+    qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%x\n", old_mode);
     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
                   env->elr_el[new_el]);