/* XXX: could force current_cpu to NULL to avoid
potential bugs */
val = ldn_p(buf, l);
- result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
+ result |= memory_region_dispatch_write(mr, addr1, val,
+ size_memop(l), attrs);
} else {
/* RAM case */
ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
/* I/O case */
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
- result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
+ result |= memory_region_dispatch_read(mr, addr1, &val,
+ size_memop(l), attrs);
stn_p(buf, l, val);
} else {
/* RAM case */
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(4), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(8), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap64(val);
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(1), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, size_memop(2), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
if (l < 4 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(4), attrs);
} else {
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
stl_p(ptr, val);
val = bswap32(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(4), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (!memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(1), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
val = bswap16(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(2), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
val = bswap64(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, size_memop(8), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);