arm64: dts: ti: k3-am64: Enable PCIe nodes at the board level

PCIe nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.

As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-7-afd@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index ef1833f65bdc612d9d9e8736c9c50a1f36b1f5cb..b193f88a7a0f76f431bbee9f2e89d3253f4a41c5 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -871,6 +871,7 @@
                ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
                         <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
                dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
+               status = "disabled";
        };
 
        pcie0_ep: pcie-ep@f102000 {
@@ -889,6 +890,7 @@
                clocks = <&k3_clks 114 0>;
                clock-names = "fck";
                max-functions = /bits/ 8 <1>;
+               status = "disabled";
        };
 
        epwm0: pwm@23000000 {

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 43d50ecfb211f83db83eb8fef7edf998d6a5d184..2dec25d9024071b2c8926275d075eea3f5eb1dc7 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -553,6 +553,7 @@
 };
 
 &pcie0_rc {
+       status = "okay";
        reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
        phys = <&serdes0_pcie_link>;
        phy-names = "pcie-phy";
@@ -563,7 +564,6 @@
        phys = <&serdes0_pcie_link>;
        phy-names = "pcie-phy";
        num-lanes = <1>;
-       status = "disabled";
 };
 
 &ecap0 {

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 8b9987ccdc1bc1a67bf5bb5c7c4326fafa4e0a61..58c71608d925b78dbc88d670c2c2cade354e8c50 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -557,14 +557,6 @@
                        <&main_r5fss1_core1_memory_region>;
 };
 
-&pcie0_rc {
-       status = "disabled";
-};
-
-&pcie0_ep {
-       status = "disabled";
-};
-
 &ecap0 {
        status = "okay";
        /* PWM is available on Pin 1 of header J3 */