.otg_port = 1,
};
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC
static u32 _fsl_readl_be(const unsigned __iomem *p)
{
return in_be32(p);
#else
#define fsl_readl(addr) readl(addr)
#define fsl_writel(val, addr) writel(val, addr)
-#endif /* CONFIG_PPC32 */
+#endif /* CONFIG_PPC */
int write_ulpi(u8 addr, u8 data)
{
if (pdata->init && pdata->init(pdev) != 0)
return -EINVAL;
+#ifdef CONFIG_PPC
if (pdata->big_endian_mmio) {
_fsl_readl = _fsl_readl_be;
_fsl_writel = _fsl_writel_be;
_fsl_readl = _fsl_readl_le;
_fsl_writel = _fsl_writel_le;
}
+#endif
/* request irq */
p_otg->irq = platform_get_irq(pdev, 0);